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ORCIDArighna Deb
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2020 – today
- 2024
[j10]Kousik Bhunia
, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars. ACM Trans. Embed. Comput. Syst. 23(6): 90:1-90:24 (2024)- [c19]Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler:
Dynamic Realization of Multiple Control Toffoli Gate. DATE 2024: 1-6 - [c18]Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das:
Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation. DSD 2024: 11-18 - [c17]Pragnya Dhal, Arighna Deb, Subrata Das, Debesh Kumar Das:
Leveraging ReRAM Sequence Graphs for Efficient Mapping of Binary Adders in ReRAM Crossbars. VDAT 2024: 1-7 - [c16]Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler:
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. VLSID 2024: 384-389 - 2023
- [j9]Kamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler:
Impact of sneak paths on in-memory logic design in memristive crossbars. it Inf. Technol. 65(1-2): 29-39 (2023) - [c15]Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. ASP-DAC 2023: 19-25 - [c14]Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler:
Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. DATE 2023: 1-6 - [c13]Subrata Das, Arighna Deb, Petr Fiser:
Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring. ISDCS 2023: 1-6 - [c12]Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler:
Verification of In-Memory Logic Design using ReRAM Crossbars. NEWCAS 2023: 1-5 - 2021
- [j8]Joyati Mondal, Arighna Deb, Debesh K. Das:
An Efficient Design for Testability Approach of Reversible Logic Circuits. J. Circuits Syst. Comput. 30(6): 2150094:1-2150094:31 (2021) - [j7]Piyalee Behera, Arighna Deb:
Design Space Exploration of Matrix-Matrix Convolution Operation. J. Circuits Syst. Comput. 30(16): 2150288:1-2150288:29 (2021) - [j6]Arighna Deb, Gerhard W. Dueck, Robert Wille:
Exploring the Potential Benefits of Alternative Quantum Computing Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1825-1835 (2021) - 2020
- [c11]Arighna Deb, Gerhard W. Dueck, Robert Wille:
Towards Exploring the Potential of Alternative Quantum Computing Architectures. DATE 2020: 682-685
2010 – 2019
- 2019
- [c10]Arighna Deb, Debesh K. Das:
Detailed Fault Model for Physical Quantum Circuits. ATS 2019: 153-158 - [c9]Sayantani Roy, Arighna Deb, Debesh K. Das:
Delay Efficient All Optical Carry Lookahead Adder. VDAT 2019: 236-244 - 2017
- [j5]Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler:
Synthesis of optical circuits using binary decision diagrams. Integr. 59: 42-51 (2017) - [j4]Arighna Deb, Debesh K. Das:
An iterative structure for synthesizing symmetric functions using quantum-dot cellular automata. Microprocess. Microsystems 53: 157-167 (2017) - [c8]Arighna Deb, Robert Wille, Rolf Drechsler:
Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs. ICCAD 2017: 233-238 - [c7]Arighna Deb, Robert Wille, Rolf Drechsler:
OR-Inverter Graphs for the Synthesis of Optical Circuits. ISMVL 2017: 278-283 - 2016
- [j3]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya:
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. ACM J. Emerg. Technol. Comput. Syst. 12(4): 34:1-34:29 (2016) - [j2]Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler:
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits. ACM J. Emerg. Technol. Comput. Syst. 13(1): 11:1-11:13 (2016) - 2015
- [c6]Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das:
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. ISMVL 2015: 14-19 - 2014
- [j1]Arighna Deb, Debesh Kumar Das, Susmita Sur-Kolay:
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic. J. Low Power Electron. 10(3): 443-454 (2014) - [c5]Arighna Deb, Debesh K. Das, Bhargab B. Bhattacharya:
Synthesis of Symmetric Boolean Functions Using a Three-Stage Network. ISED 2014: 182-186 - [c4]Arighna Deb, Debesh Kumar Das:
A regular network of symmetric functions in quantum-dot cellular automata. VDAT 2014: 1-6 - 2013
- [c3]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya:
Reversible synthesis of symmetric boolean functions based on unate decomposition. ACM Great Lakes Symposium on VLSI 2013: 351-352 - [c2]Arighna Deb, Debesh K. Das, Susmita Sur-Kolay:
Modular Design for Symmetric Functions Using Quantum Quaternary Logic. ISED 2013: 143-147 - [c1]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler:
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. RC 2013: 182-195
Coauthor Index
aka: Debesh K. Das
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