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ORCIDSallar Ahmadi-Pour
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2020 – today
- 2024
[j3]Sajjad Parvin
, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Lower the RISC: Designing optical-probing-attack-resistant cores. Microprocess. Microsystems 111: 105121 (2024)- [c11]Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler:
Security Coverage Metrics for Information Flow at the System Level. ASPDAC 2024: 945-950 - [c10]Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler:
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. DAC 2024: 349:1-349:2 - [c9]Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler:
LLM-Guided Formal Verification Coupled with Mutation Testing. DATE 2024: 1-2 - [c8]Mohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri:
Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study. NorCAS 2024: 1-7 - [c7]Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. VLSID 2024: 577-582 - 2023
- [j2]Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2635-2639 (2023) - [c6]Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. COINS 2023: 1-4 - [c5]Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. FDL 2023: 1-8 - [i1]Sallar Ahmadi-Pour, Pascal Pieper, Rolf Drechsler:
Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap. CoRR abs/2311.00442 (2023) - 2022
- [j1]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. J. Syst. Archit. 133: 102757 (2022) - [c4]Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier:
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. DSD 2022: 134-141 - 2021
- [c3]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. FDL 2021: 1-7 - [c2]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. MBMV 2021: 1-8
2010 – 2019
- 2019
- [c1]Hendra Kesuma, Sallar Ahmadi-Pour, Hans-Jürgen Zimmerman, Amber Joseph, Patrick Weis:
Ultrasonic Wireless Sensor Network for Human Habitation in Deep Space Mission. WiSEE 2019: 122-127
Coauthor Index
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