research-article

An MIG-based compiler for programmable logic-in-memory architectures

Authors:

Mathias Soeken,

Saeideh Shirinzadeh,

Pierre-Emmanuel Gaillardon,

Luca Gaetano Amarú,

Rolf Drechsler,

Giovanni De MicheliAuthors Info & Claims

DAC '16: Proceedings of the 53rd Annual Design Automation Conference

Article No.: 117, Pages 1 - 6

https://doi.org/10.1145/2897937.2897985

Published: 05 June 2016 Publication History

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Abstract

Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture solely based on resistive memory arrays. Our approach uses Majority-Inverter Graphs (MIGs) to manage the computational operations. In order to obtain a performance and resource efficient program, we employ optimization techniques both to the underlying MIG as well as to the compilation procedure itself. In addition, our proposed approach optimizes the program with respect to memory endurance constraints which is of particular importance for in-memory computing architectures.

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DAC '16: Proceedings of the 53rd Annual Design Automation Conference

June 2016

1048 pages

ISBN:9781450342360

DOI:10.1145/2897937

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 05 June 2016

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DAC '16

DAC '16: The 53rd Annual Design Automation Conference 2016

June 5 - 9, 2016

Texas, Austin

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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https://doi.org/10.23919/DATE58400.2024.10546754
Froehlich SDrechsler R(2022)LiM-HDL: HDL-Based Synthesis for In-Memory Computing2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774627(1395-1400)Online publication date: 14-Mar-2022
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Froehlich SShirinzadeh SDrechsler R(2022)Parallel Computing of Graph-based Functions in ReRAMACM Journal on Emerging Technologies in Computing Systems10.1145/345316318:2(1-24)Online publication date: 12-Jan-2022
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Endurance management for resistive logic-in-memory computing architectures

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations

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