Article

A switch architecture and signal synchronization for GALS system-on-chips

Authors:

Heiko Hinkelmann,

Manfred GlesnerAuthors Info & Claims

SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

Pages 210 - 215

https://doi.org/10.1145/1016568.1016625

Published: 04 September 2004 Publication History

Abstract

Increasing power consumption and growing design effort are considered limiting factors in the design of chip-wide synchronous System-on-Chip designs. The attempt to get over these problems leads to an intensified look at asynchronous communication solutions, sometimes based on Network-on-Chips. Despite this basically asynchronous approach, most of the actual research work is not supporting a globally genuinely-asynchronous solution. We present a modular switch for a true globally asynchronous interconnect network. Independent clock generators in each switch maintain a local clock thus avoiding a global clock at the level of the interconnect network. The general switch architecture is described and the integration of the synchronization technique used to resolve metastability is discussed in detail. First synthesis results of a prototypical VLSI implementation are presented.

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Cited By

Liu HCao FLiu DZou XZhang Z(2010)A methodology for design of unbuffered router microarchitecture for S-mesh NoCProceedings of the 2010 IFIP international conference on Network and parallel computing10.5555/1882011.1882056(442-451)Online publication date: 13-Sep-2010
https://dl.acm.org/doi/10.5555/1882011.1882056
Liu HCao FLiu DZou XZhang Z(2010)A Methodology for Design of Unbuffered Router Microarchitecture for S-Mesh NoCNetwork and Parallel Computing10.1007/978-3-642-15672-4_37(442-451)Online publication date: 2010
https://doi.org/10.1007/978-3-642-15672-4_37
Miro Panades IGreiner A(2007)Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS ArchitecturesProceedings of the First International Symposium on Networks-on-Chip10.1109/NOCS.2007.14(83-94)Online publication date: 7-May-2007
https://dl.acm.org/doi/10.1109/NOCS.2007.14
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Index Terms

A switch architecture and signal synchronization for GALS system-on-chips
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Integrated circuits
    1. Interconnect

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Published In

cover image ACM Conferences

SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

September 2004

296 pages

ISBN:1581139470

DOI:10.1145/1016568

General Chair:
Edna Natividade da Silva Barros
Federal University of Pernambuco, Brazil
,
Program Chairs:
Flàvio Rech Wagner
Federal University of Rio Grande do Sul, Brazil
,
Luigi Carro
Federal University of Rio Grande do Sul, Brazil
,
Franz Josef Rammig
University of Paderborn, Germany

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 04 September 2004

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SBCCI04

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SBCCI04: 17th Symposium on Integrated Circuits and System Design

September 7 - 11, 2004

Pernambuco, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Liu HCao FLiu DZou XZhang Z(2010)A methodology for design of unbuffered router microarchitecture for S-mesh NoCProceedings of the 2010 IFIP international conference on Network and parallel computing10.5555/1882011.1882056(442-451)Online publication date: 13-Sep-2010
https://dl.acm.org/doi/10.5555/1882011.1882056
Liu HCao FLiu DZou XZhang Z(2010)A Methodology for Design of Unbuffered Router Microarchitecture for S-Mesh NoCNetwork and Parallel Computing10.1007/978-3-642-15672-4_37(442-451)Online publication date: 2010
https://doi.org/10.1007/978-3-642-15672-4_37
Miro Panades IGreiner A(2007)Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS ArchitecturesProceedings of the First International Symposium on Networks-on-Chip10.1109/NOCS.2007.14(83-94)Online publication date: 7-May-2007
https://dl.acm.org/doi/10.1109/NOCS.2007.14
Bouhraoua AElrabaa M(2006)A High-Throughput Network-on-Chip Architecture for Systems-on-Chip Interconnect2006 International Symposium on System-on-Chip10.1109/ISSOC.2006.321984(1-4)Online publication date: Nov-2006
https://doi.org/10.1109/ISSOC.2006.321984
Bouhraoua AElrabaa M(2006)An Efficient Network-on-Chip Architecture Based on the Fat-Tree (FT) Topology2006 International Conference on Microelectronics10.1109/ICM.2006.373259(28-31)Online publication date: Dec-2006
https://doi.org/10.1109/ICM.2006.373259
Wang XAhonen TNurmi J(2006)Prototyping a Globally Asynchronous Locally Synchronous Network-On-Chip on a Conventional FPGA Device Using Synchronous Design Tools2006 International Conference on Field Programmable Logic and Applications10.1109/FPL.2006.311284(1-6)Online publication date: Aug-2006
https://doi.org/10.1109/FPL.2006.311284
Glesner MHinkelmann HHollstein TIndrusiak LMurgan TObeid APetrov MPionteck TZipf P(2005)Reconfigurable embedded systemsProceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation10.1007/11512622_3(12-21)Online publication date: 18-Jul-2005
https://dl.acm.org/doi/10.1007/11512622_3

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