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ORCIDICCD 2006: San Jose, CA, USA
- 24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA. IEEE 2006, ISBN 978-0-7803-9707-1
Keynote Presentation
- William J. Dally:
Computer Architecture in the Many-Core Era. 1
Microarchitecture Optimization
- Fei Gao, Suleyman Sair:
Long-term Performance Bottleneck Analysis and Prediction. 3-9 - Weifeng Zhang, Brad Calder, Dean M. Tullsen
, Steve Checkoway:
Speculative Code Value Specialization Using the Trace Cache Fill Unit. 10-16 - Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Mahapatra:
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses. 17-24 - Shuo Wang, Lei Wang:
Joint Performance Improvement and Error Tolerance for Memory Design Based on Soft Indexing. 25-30 - Chuanjun Zhang:
A Low Power Highly Associative Cache for Embedded Systems. 31-36
1.2 Timing Analysis
- Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri:
On the Improvement of Statistical Static Timing Analysis. 37-42 - Debasish Das, Ahmed Shebaita, Hai Zhou, Yehea I. Ismail, Kip Killpack:
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. 43-49 - Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier:
Reduction of Crosstalk Pessimism using Tendency Graph Approach. 50-55 - Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan:
Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation. 56-62
1.3 Advanced Circuits and Interconnections
- Simon Hollis, Simon W. Moore:
RasP: An Area-efficient, On-chip Network. 63-69 - Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Quantitative Prediction of On-chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects. 70-75 - Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri:
CMOS Comparators for High-Speed and Low-Power Applications. 76-81 - Mehrdad Nourani, Deepak S. Vijayasarathi, Poras T. Balsara:
Reconfigurable CAM Architecture for Network Search Engines. 82-87 - Karl Mohr, Lawrence Clark:
Delay and Area Efficient First-level Cache Soft Error Detection and Correction. 88-92
2.1 Special Session on Nanotechnology - I
- Krishnendu Chakrabarty:
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD. 93-100
3.1 Technology-Aware Design
- Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum:
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. 101-107 - Subramanian Ramaswamy, Sudhakar Yalamanchili:
Customizable Fault Tolerant Caches for Embedded Processors. 108-113 - Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang:
Reduce Register Files Leakage Through Discharging Cells. 114-119 - Yi Ma, Huiyang Zhou:
Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution. 120-126
3.2 Multiprocessors and Systems-on-Chip
- Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar:
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. 127-133 - Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li, Li-Shiuan Peh:
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks. 134-141 - Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessabi, Hamid Sarbazi-Azad:
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips. 142-147 - Sean Leventhal, Manoj Franklin:
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors. 148-154
3.3 Robust and Low-Power Design Styles
- Kimiyoshi Usami, Naoaki Ohkubo:
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals. 155-161 - Kim Yaw Tong, Lawrence T. Pileggi:
Design Methodology of Regular Logic Bricks for Robust Integrated Circuits. 162-167 - Sanjay Pant, David T. Blaauw:
An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. 168-173 - Zhiyi Yu, Bevan M. Baas:
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. 174-179
Banquet - Keynote Speaker
- Fabio Angelillis:
Scaling Manufacturability Software to Thousands of Processors. 2
Special Session on Interconnect
- Enno Wein:
Scale in Chip Interconnect requires Network Technology . 180-186 - Uri Cummings:
Interconnect Considerations For High Performance Network on Chip Designs. 187 - Drew Wingard:
Addressing Multicore Communication Challenges Using NoC Technology. 188
5.1 Hardware and Software Scheduling Techniques
- Edson Borin, Maurício Breternitz Jr., Youfeng Wu, Guido Araujo:
Clustering-Based Microcode Compression. 189-196 - Kuo-Su Hsiao, Chung-Ho Chen:
Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling. 197-202 - Ruben Gran Tejero, Enric Morancho, Àngel Olivé, José María Llabería:
An Enhancement for a Scheduling Logic Pipelined over two Cycles . 203-209
5.2 Nanoscale Modeling + Synthesis
- Saraju P. Mohanty, Elias Kougianos:
Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates. 210-215 - Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. 216-221 - Rasit Onur Topaloglu, Andrew B. Kahng:
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction. 222-229
5.3 Power Issues in Test
- Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses. 230-236 - Ho Fai Ko, Nicola Nicolici:
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints. 237-242 - Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker:
Power Droop Testing. 243-250 - Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. 251-258
Special Session on Hardware Equivalence
- Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen:
Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . 259-266 - Daher Kaiss, Silvian Goldenberg, Zurab Khasidashvili:
Seqver : A Sequential Equivalence Verifier for Hardware Designs . 267-273 - Alan Hu:
High-Level vs. RTL Combinational Equivalence: An Introduction. 274-279
7.1 Functional Verification - Advances and Applications
- Kameshwar Chandrasekar, Michael S. Hsiao:
Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique. 280-285 - Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten:
Requirements and Concepts for Transaction Level Assertions. 286-293 - Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. 294-299 - Charles H.-P. Wen, Onur Guzey, Li-C. Wang:
Simulation-based functional test justification using a decision-digram-based Boolean data miner. 300-307
7.2 Application Specific Processing Elements
- Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner:
FPGA Implementation of High Speed FIR Filters Using Add and Shift Method. 308-313 - Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi:
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. 314-319 - Tinoosh Mohsenin, Bevan M. Baas:
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. 320-325 - Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi:
An Efficient, Scalable Hardware Engine for Boolean SATisfiability. 326-331
7.3 Physical Design
- Hailin Jiang, Malgorzata Marek-Sadowska:
Power/ground supply network optimization for power-gating. 332-337 - Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu:
A Pattern Generation Technique for Maximizing Power Supply Currents. 338-343 - Avijit Dutta, David Z. Pan:
Partial Functional Manipulation Based Wirelength Minimization. 344-349 - Sungjae Kim, Eugene Shragowitz:
Iterative-Constructive Standard Cell Placer for High Speed and Low Power. 350-355
8.1 Design Techniques and Methods
- Bita Gorjiara, Mehrdad Reshadi, Daniel Gajski:
Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths . 356-361 - Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi:
Assertion-Based Microarchitecture Design for Improved Reliability. 362-369 - Xinmiao Zhang:
High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding. 370-375
8.2 System On Chip Design
- Banit Agrawal, Timothy Sherwood:
Guiding Architectural SRAM Models. 376-382 - Jinwen Xi, Peixin Zhong:
A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models. 383-388 - Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
Reliability Support for On-Chip Memories Using Networks-on-Chip. 389-396 - Shaobo Liu, Qinru Qiu, Qing Wu:
Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems. 397-404
8.3 Power-Efficient Systems
- Chuanjun Zhang:
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems. 405-410 - Xiaofang Wang, Sotirios G. Ziavras:
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors. 411-416 - Frederick A. Ware, Craig Hampel:
Improving Power and Data Efficiency with Threaded Memory Modules. 417-424
9.1 Improving test quality
- Chia Yee Ooi, Hideo Fujiwara:
A New Class of Sequential Circuits with Acyclic Test Generation Complexity. 425-431 - Erkan Acar, Sule Ozev:
Efficient Testing of RF MIMO Transceivers Used in WLAN Applications. 432-437 - Shideh Shahidi, Sandeep K. Gupta:
A theory of Error-Rate Testing. 438-445 - Dong Xiang, Kaiwei Li, Hideo Fujiwara, Jiaguang Sun:
Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. 446-451
9.2 Architectural Synthesis
- Hwisung Jung, Massoud Pedram:
Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach. 452-457 - Fu-Chiung Cheng, Hung-Chi Wu:
Design and Implementation of Software Objects in Hardware. 458-463 - Sourav Roy, Rajat Bhatia, Ashish Mathur:
An accurate Energy estimation framework for VLIW Processor Cores. 464-469
10.1 Design Practice
- Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler:
Design and Implementation of the TRIPS Primary Memory System. 470-476 - Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger:
Implementation and Evaluation of On-Chip Network Architectures. 477-484 - Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang:
Microarchitecture and Performance Analysis of Godson-2 SMT Processor. 485-490 - Satish Narayanasamy, Bruce Carneal, Brad Calder:
Patching Processor Design Errors. 491-498
10.2 Architectural Support for Error Protection
- Nathan Sadler, Daniel J. Sorin:
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache. 499-505 - Yixin Shi, Sean Dempsey, Gyungho Lee:
Architectural Support for Run-Time Validation of Control Flow Transfer. 506-513 - Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Saurabh Bagchi:
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection. 514-521
11.1 Special Session on Nanotechnology - II
- R. Iris Bahar:
Trends and Future Directions in Nano Structure Based Computing and Fabrication. 522-527
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