Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID14th ARC 2018: Santorini, Greece
- Nikolaos S. Voros, Michael Hübner, Georgios Keramidas, Diana Goehringer, Christos P. Antonopoulos, Pedro C. Diniz:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings. Lecture Notes in Computer Science 10824, Springer 2018, ISBN 978-3-319-78889-0
Machine Learning and Neural Networks
- Michalis Rizakis, Stylianos I. Venieris
, Alexandros Kouris, Christos-Savvas Bouganis:
Approximate FPGA-Based LSTMs Under Computation Time Constraints. 3-15 - Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. 16-28 - Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. 29-42 - Kazusa Musha, Tomohiro Kudoh, Hideharu Amano:
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud. 43-54 - Panagiotis G. Mousouliotis, Loukas P. Petrou:
SqueezeJet: High-Level Synthesis Accelerator Design for Deep Convolutional Neural Networks. 55-66 - Konstantinos Katsantonis, Christoforos Kachris, Dimitrios Soudris:
Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering. 67-78
FPGA-Based Design and CGRA Optimizations
- Oguzhan Sezenlik, Sebastian Schüller, Joachim K. Anlauf:
VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express. 81-92 - Lukas Johannes Jung, Christian Hochberger:
Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling. 93-104 - Kalindu Herath, Alok Prakash, Thambipillai Srikanthan:
Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network. 105-118 - Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan:
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. 119-131 - Junsik Kim, Jaehyun Park:
FPGA-Based Memory Efficient Shift-And Algorithm for Regular Expression Matching. 132-141 - Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano:
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study. 142-150
Applications and Surveys
- Tim Hansmeier, Marco Platzner, David Andrews:
An FPGA/HMC-Based Accelerator for Resolution Proof Checking. 153-165 - Almabrok Abdoalnasir, Mihalis Psarakis, Anastasios I. Dounis:
An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm. 166-177 - Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy:
ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs. 178-191 - Masahiro Fukuda, Yasushi Inoguchi:
FPGA-Based Parallel Pattern Matching. 192-203 - Deepayan Bhowmik, Kofi Appiah:
Embedded Vision Systems: A Review of the Literature. 204-216 - Emmanuel Ofori-Attah, Xiaohang Wang, Michael Opoku Agyeman:
A Survey of Low Power Design Techniques for Last Level Caches. 217-228
Fault-Tolerance, Security and Communication Architectures
- Augusto G. Erichsen, Anderson Luiz Sartor, Jeckson Dellagostin Souza, Monica Magalhães Pereira, Stephan Wong, Antonio C. S. Beck:
ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores. 231-242 - Fabio Benevenuti, Fernanda Lima Kastensmidt:
Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft Errors. 243-254 - Milind Parelkar, Darshan Jetly:
High Performance UDP/IP 40Gb Ethernet Stack for FPGAs. 255-268 - Christos P. Antonopoulos, Konstantinos Antonopoulos, Christos Panagiotou, Nikolaos S. Voros:
Tackling Wireless Sensor Network Heterogeneity Through Novel Reconfigurable Gateway Approach. 269-280 - Bruno da Silva, Laurent Segers, An Braeken, Kris Steenhaut, Abdellah Touhafi:
A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks. 281-293 - Lampros Pyrgas, Paris Kitsos:
A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing. 294-303 - Raheel Afsharmazayejani, Fahimeh Yazdanpanah, Amin Rezaei, Mohammad Alaei, Masoud Daneshtalab:
HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era. 304-316
Reconfigurable and Adaptive Architectures
- Luca Sterpone, Ludovica Bozzoli:
Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach. 319-330 - Benedikt Janßen, Florian Kästner, Tim Wingender, Michael Hübner:
A Dynamic Partial Reconfigurable Overlay Framework for Python. 331-342 - Osvaldo Navarro, Michael Hübner:
Runtime Adaptive Cache for the LEON3 Processor. 343-354 - Rafael Fão de Moura, Michael Guilherme Jordan, Antonio Carlos Schneider Beck, Mateus Beck Rutzig:
Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture. 355-366 - Jeckson Dellagostin Souza, Anderson Luiz Sartor, Luigi Carro, Mateus Beck Rutzig, Stephan Wong, Antonio C. S. Beck:
DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability. 367-378 - Kamil Piszczek, Piotr Janus, Tomasz Kryjak:
The Use of HACP+SBT Lossless Compression in Optimizing Memory Bandwidth Requirement for Hardware Implementation of Background Modelling Algorithms. 379-391 - Sikandar Khan, Kyprianos Papadimitriou, Giorgio C. Buttazzo, Kostas Kalaitzakis:
A Reconfigurable PID Controller. 392-403
Design Methods and Fast Prototyping
- Jens Rettkowski, Diana Goehringer:
High-Level Synthesis of Software-Defined MPSoCs. 407-419 - Björn Liebig, Julian Oppermann, Oliver Sinnen, Andreas Koch:
Improved High-Level Synthesis for Complex CellML Models. 420-432 - Habib ul Hasan Khan, Ahmed Kamal, Diana Goehringer:
An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors. 433-445 - Julián Caba, João M. P. Cardoso, Fernando Rincón, Julio Dondo, Juan Carlos López:
Rapid Prototyping and Verification of Hardware Modules Generated Using HLS. 446-458 - Konstantinos Georgopoulos, Pavlos Malakonakis, Nikolaos Tampouratzis, Antonis Nikitakis, Grigorios Chrysos, Apostolos Dollas, Dionysios N. Pnevmatikatos, Ioannis Papaefstathiou:
Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design. 459-470 - Kris Heid, Jakob Wenzel, Christian Hochberger:
Fast DSE for Automated Parallelization of Embedded Legacy Applications. 471-484 - Augusto W. Hoppe, Fernanda Lima Kastensmidt, Jürgen Becker:
Control Flow Analysis for Embedded Multi-core Hybrid Systems. 485-496
FPGA-Based Design and Applications
- Pedro Henrique Exenberger Becker, Anderson Luiz Sartor, Marcelo Brandalero, Tiago Trevisan Jost, Stephan Wong, Luigi Carro, Antonio C. S. Beck:
A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs. 499-510 - Mário Lopes Ferreira, João Canas Ferreira, Michael Hübner:
A Parallel-Pipelined OFDM Baseband Modulator with Dynamic Frequency Scaling for 5G Systems. 511-522 - Paulo Garcia, Deepayan Bhowmik, Andrew M. Wallace, Robert J. Stewart, Greg Michaelson:
Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems. 523-536 - Ayan Palchaudhuri, Anindya Sundar Dhar:
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs. 537-550 - Umar Ibrahim Minhas, Roger F. Woods, George Karakonstantis:
Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations. 551-563 - Santhi Natarajan, N. Krishna Kumar, H. V. Anuchan, Debnath Pal, S. K. Nandy:
ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads. 564-577 - Zhenhua Guo, Baoyu Fan, Yaqian Zhao, Xuelei Li, Shixin Wei, Long Li:
An OpenCLTM Implementation of WebP Accelerator on FPGAs. 578-589 - Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima:
Efficient Multitasking on FPGA Using HDL-Based Checkpointing. 590-602 - Uzaif Sharif, Shahnam Mirzaei:
High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware. 603-614 - Johannes Pfau, Shalina Percy Delicia Figuli, Steffen Bähr, Jürgen Becker:
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems. 615-626 - Peter Littlewood, Shahnam Mirzaei, Krishna Murthy Kattiyan Ramamoorthy:
Reconfigurable IP-Based Spectral Interference Canceller. 627-639 - Nikolaos Tzanis, Grigorios Proiskos, Michael K. Birbas, Alexios N. Birbas:
FPGA-Assisted Distribution Grid Simulator. 640-646 - Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Alberto Bosio:
Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs. 647-658
Special Session: Research Projects
- Florian Fricke, André Werner, Keyvan Shahin, Michael Hübner:
CGRA Tool Flow for Fast Run-Time Reconfiguration. 661-672 - Christoforos Kachris, Ioannis Stamelos, Elias Koromilas, Dimitrios Soudris:
Seamless FPGA Deployment over Spark in Cloud Computing: A Use Case on Machine Learning Hardware Acceleration. 673-684 - Jürgen Becker, Falco K. Bapp:
The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications. 685-699 - Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller, Umut Durak, Jürgen Becker:
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. 700-711 - Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros, Michael Hübner, Fynn Schwiegelshohn, Diana Goehringer, Maria Dagioglou, Georgios Stavrinos, Stasinos Konstantopoulos, Vangelis Karkaletsis:
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience. 712-723 - Pavlos Malakonakis, Konstantinos Georgopoulos, Aggelos Ioannou, Luciano Lavagno, Ioannis Papaefstathiou, Iakovos Mavroidis:
HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE. 724-736 - Ahmad Sadek, Ananya Muddukrishna, Lester Kalms, Asbjørn Djupdal, Ariel Podlubne, Antonio Paolillo, Diana Goehringer, Magnus Jahre:
Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview. 737-749
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-08-16 18:18 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
