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2020 – today
- 2024
[j47]Vu Trung Duong Le, Hoai-Luan Pham
, Thi Hong Tran, Yasuhiko Nakashima:
Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 319-330 (2024)- [j46]Takumi Kuwahara, Reon Oshio, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima:
Fusion synapse by memristor and capacitor for spiking neuromorphic systems. Neurocomputing 593: 127792 (2024) - [j45]Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima:
A Compressed Spiking Neural Network Onto a Memcapacitive In-Memory Computing Array. IEEE Micro 44(1): 8-16 (2024) - [j44]Hoai Luan Pham, Vu Trung Duong Le, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima:
LiCryptor: High-Speed and Compact Multi-Grained Reconfigurable Accelerator for Lightweight Cryptography. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4624-4637 (2024) - [j43]Yan Chen, Renyuan Zhang, Yirong Kan, Sa Yang, Yasuhiko Nakashima:
Bisection Neural Network Toward Reconfigurable Hardware Implementation. IEEE Trans. Neural Networks Learn. Syst. 35(3): 3663-3673 (2024) - [c106]Dohyun Kim, Koki Asahina, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima:
Power-Efficient Acceleration of GCNs on Coarse-Grained Linear Arrays. COOL CHIPS 2024: 1-5 - [c105]Pham Hoai Luan, Hai Hau Nguyen, Vu Trung Duong Le, Thi Diem Tran, Tuan Hai Vu, Thi Hong Tran, Yasuhiko Nakashima:
MRCA: Multi-grained Reconfigurable Cryptographic Accelerator for Diverse Security Requirements. COOL CHIPS 2024: 1-6 - [c104]Mingyang Li, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima:
A Fully-Parallel Reconfigurable Spiking Neural Network Accelerator with Structured Sparse Connections. ISCAS 2024: 1-5 - [c103]Ngoc Hung Nguyen, Duc Hong An Le, Vu Trung Duong Le, Van Tinh Nguyen, Tuan Hai Vu, Hoai Luan Pham, Yasuhiko Nakashima:
LI-RV: A Fast and Efficient RISC-V based Coprocessor for Lightweight Cryptography. ISOCC 2024: 1-2 - [c102]Pham Hoai Luan, Vu Trung Duong Le, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima:
CGLA: Coarse-Grained Linear Array for Multi-Hash Acceleration in Blockchain Mining. ISOCC 2024: 93-94 - [c101]Vu Trung Duong Le, Hoai Luan Pham, Tuan Hai Vu, Van Duy Tran, Thi Diem Tran, Yasuhiko Nakashima:
UCP: A Unified Cryptographic Processor for High Performance and Low Power Security Applications. ISOCC 2024: 95-96 - [c100]Duc Hong An Le, Vu Trung Duong Le, Viet Anh Ho, Van Tinh Nguyen, Hoai Luan Pham, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima:
High-Efficiency RISC-V-Based Cryptographic Coprocessor for Security Applications. ISOCC 2024: 103-104 - [c99]Vu Tuan Hai, Vo Minh Kiet, Vu Trung Duong Le, Pham Hoai Luan, Le Bin Ho, Yasuhiko Nakashima:
Quantum Battery Optimization through Quantum Machine Learning Techniques. ISOCC 2024: 121-122 - [c98]Nhat Nguyen Dinh, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Yasuhiko Nakashima:
Kyberator: A High-Efficiency FPGA-Based Multi-Mode CRYSTALS-Kyber Accelerator for Quantum-Resistant Security Applications. ISOCC 2024: 308-309 - [i5]Van Duy Tran, Tran Xuan Hieu Le, Thi Diem Tran, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Tinh Nguyen, Yasuhiko Nakashima:
Exploring the Limitations of Kolmogorov-Arnold Networks in Classification: Insights to Software Training and Hardware Implementation. CoRR abs/2407.17790 (2024) - 2023
- [j42]Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications. IEEE Des. Test 40(5): 15-25 (2023) - [j41]Van-Cam Nguyen, Yasuhiko Nakashima:
Implementation of Fully-Pipelined CNN Inference Accelerator on FPGA and HBM2 Platform. IEICE Trans. Inf. Syst. 106(6): 1117-1129 (2023) - [j40]Mutsumi Kimura, Yuma Ishisaki, Yuta Miyabe, Homare Yoshida, Isato Ogawa, Tomoharu Yokoyama, Ken-Ichi Haga, Eisuke Tokumitsu, Yasuhiko Nakashima:
Neuromorphic System Using Memcapacitors and Autonomous Local Learning. IEEE Trans. Neural Networks Learn. Syst. 34(5): 2366-2373 (2023) - [c97]Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima:
Efficient and High-Speed CGRA Accelerator for Cryptographic Applications. candar 2023: 189-195 - [c96]Shihori Akane, Isao Horiuchi, Yasushi Hiroshima, Yasuhiko Nakashima, Mutsumi Kimura:
Phase-Change Memory using Cu2GeTe3 and Multiple Writing Technique for Neuromorphic Systems. ICCE 2023: 1-5 - [c95]Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Quoc Duy Nam Nguyen, Thi Sang Duong, Yasuhiko Nakashima:
Versatile Resource-shared Cryptographic Accelerator for Multi-Domain Applications. ICICDT 2023: 104-107 - [c94]Vu Trung Duong Le, Hoai Luan Pham, Thi Sang Duong, Thi Hong Tran, Quoc Duy Nam Nguyen, Yasuhiko Nakashima:
RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms. KSE 2023: 1-6 - [c93]Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Diem Tran, Ren Imamura, Quoc Duy Nam Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission. MCSoC 2023: 419-425 - [c92]Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Thi Sang Duong, Yasuhiko Nakashima:
High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing. MCSoC 2023: 576-583 - [c91]Ren Imamura, Guangxian Zhu, Thi Sang Duong, Hoai Luan Pham, Renyuan Zhang, Yasuhiko Nakashima:
Energy-Efficient 3D Convolution Using Interposed Memory Accelerator eXtension 2 for Medical Image Processing. MICAD 2023: 62-71 - [c90]Pham Hoai Luan, Thi Sang Duong, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima:
Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain. MWSCAS 2023: 355-359 - [c89]Tomoya Akabe, Ryotaro Funai, Yasuhiko Nakashima:
Sensitivity Analysis of Memory Bandwidth on Column-superposed Versatile Linear CGRA. NEWCAS 2023: 1-5 - [c88]Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima:
An Ultra-Compact Calculation Unit with Temporal-Spatial Re-configurability. NEWCAS 2023: 1-5 - [c87]Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Ren Imamura, Thi Hong Tran, Yasuhiko Nakashima:
Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing. RIVF 2023: 124-129 - [c86]Thi Sang Duong, Hoai Luan Pham, Vu Trung Duong Le, Thi Hong Tran, Yasuhiko Nakashima:
Power-Efficient and Programmable Hashing Accelerator for Massive Message Processing. SOCC 2023: 1-6 - [c85]Babak Golbabaei, Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima:
A Non-deterministic Training Approach for Memory-Efficient Stochastic Neural Networks. SOCC 2023: 1-6 - [c84]Reon Oshio, Takumi Kuwahara, Mutsumi Kimura, Yasuhiko Nakashima:
Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory Computing. SOCC 2023: 1-6 - 2022
- [j39]Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator. IEEE Access 10: 11830-11845 (2022) - [j38]Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
Compact Message Permutation for a Fully Pipelined BLAKE-256/512 Accelerator. IEEE Access 10: 68740-68754 (2022) - [j37]Mutsumi Kimura, Hiroki Yamanaka, Yasuhiko Nakashima:
Application of Machine Learning to Environmental DNA Metabarcoding. IEEE Access 10: 101790-101794 (2022) - [j36]Hiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima:
GPGPU Implementation of Variational Bayesian Gaussian Mixture Models. IEICE Trans. Inf. Syst. 105-D(3): 611-622 (2022) - [j35]Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima:
A Hybrid Bayesian-Convolutional Neural Network for Adversarial Robustness. IEICE Trans. Inf. Syst. 105-D(7): 1308-1319 (2022) - [j34]Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima:
MuGRA: A Scalable Multi-Grained Reconfigurable Accelerator Powered by Elastic Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 258-271 (2022) - [c83]Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima:
A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training. COOL CHIPS 2022: 1-6 - [c82]Hoai Luan Pham, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A Coarse Grained Reconfigurable Architecture for SHA-2 Acceleration. IPDPS Workshops 2022: 671-678 - [c81]Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A High-Efficiency FPGA-based BLAKE-256 Accelerator for Securing Blockchain Networks. MWSCAS 2022: 1-4 - [c80]Vu Trung Duong Le, Pham Hoai Luan, Thi Hong Tran, Yasuhiko Nakashima:
CSIP: A Compact Scrypt IP design with single PBKDF2 core for Blockchain mining. SBCCI 2022: 1-6 - [c79]Pham Hoai Luan, Thi Hong Tran, Vu Trung Duong Le, Yasuhiko Nakashima:
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications. SBCCI 2022: 1-6 - [c78]Hiroki Nishimoto, Renyuan Zhang, Yasuhiko Nakashima:
Application and Evaluation of Quantization for Narrow Bit-width Resampling of Sequential Monte Carlo. SOCC 2022: 1-6 - [c77]Man Wu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima:
GAND-Nets: Training Deep Spiking Neural Networks with Ternary Weights. SOCC 2022: 1-6 - [c76]Guangxian Zhu, Huijia Wang, Yirong Kan, Zheng Chen, Ming Huang, Md. Altaf-Ul-Amin, Naoaki Ono, Shigehiko Kanaya, Renyuan Zhang, Yasuhiko Nakashima:
A Stochastic Coding Method of EEG Signals for Sleep Stage Classification. SOCC 2022: 1-6 - 2021
- [j33]Thi Hong Tran, Hoai Luan Pham, Yasuhiko Nakashima:
A High-Performance Multimem SHA-256 Accelerator for Society 5.0. IEEE Access 9: 39182-39192 (2021) - [j32]Van-Tinh Nguyen, Quang-Kien Trinh, Renyuan Zhang, Yasuhiko Nakashima:
STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM. IEEE Access 9: 151373-151385 (2021) - [j31]Vu Trung Duong Le, Thi Hong Tran, Hoai Luan Pham, Duc Khai Lam, Yasuhiko Nakashima:
MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security. IEEE Access 9: 168383-168396 (2021) - [j30]Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima:
A Feasibility Study of Multi-Domain Stochastic Computing Circuit. IEICE Trans. Electron. 104-C(5): 153-163 (2021) - [j29]Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima:
Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks. IEICE Trans. Inf. Syst. 104-D(11): 1981-1991 (2021) - [j28]Man Wu, Yirong Kan, Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima:
DiaNet: An elastic neural network for effectively re-configurable implementation. Neurocomputing 464: 242-251 (2021) - [j27]Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima:
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing. Integr. 77: 180-192 (2021) - [j26]Thi Hong Tran, Hoai Luan Pham, Tri Dung Phan, Yasuhiko Nakashima:
BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4245-4258 (2021) - [c75]Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory. COOL CHIPS 2021: 1-3 - [c74]Sugahara Takuya, Renyuan Zhang, Yasuhiko Nakashima:
Training Low-Latency Spiking Neural Network through Knowledge Distillation. COOL CHIPS 2021: 1-3 - [c73]Reon Oshio, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima:
Preliminary Evaluation for Multi-domain Spike Coding on Memcapacitive Neuromorphic Circuit. CANDAR (Workshops) 2021: 114-119 - [c72]Van-Cam Nguyen, Yasuhiko Nakashima:
Analysis of Fully-Pipelined CNN Implementation on FPGA and HBM2. CANDAR (Workshops) 2021: 134-137 - [c71]Tomoya Akabe, Renyuan Zhang, Yasuhiko Nakashima:
Speeding Up of CGRAs by Reshaping and Stochastic FMA. CANDAR (Workshops) 2021: 272-277 - [c70]Van-Tinh Nguyen, Tieu-Khanh Luong, Emanuel M. Popovici, Quang-Kien Trinh, Renyuan Zhang, Yasuhiko Nakashima:
An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic. MWSCAS 2021: 386-390 - 2020
- [j25]Hoai Luan Pham, Thi Hong Tran, Tri Dung Phan, Vu Trung Duong Le, Duc Khai Lam, Yasuhiko Nakashima:
Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining. IEEE Access 8: 139634-139646 (2020) - [j24]Jun Iwamoto, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima:
Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth. IEICE Trans. Inf. Syst. 103-D(3): 578-589 (2020) - [j23]Ryuta Shingai, Yuria Hiraga, Hisakazu Fukuoka, Takamasa Mitani, Takashi Nakada, Yasuhiko Nakashima:
Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing. IEICE Trans. Inf. Syst. 103-D(10): 2072-2082 (2020) - [c69]Taku Honda, Hiroki Nishimoto, Yasuhiko Nakashima:
Speeding Up VBGMM By Using Logsumexp With the Approximate Exp-function. CANDAR (Workshops) 2020: 113-115 - [c68]Thi Thu Thao Khong, Takashi Nakada, Yasuhiko Nakashima:
Bayes without Bayesian Learning for Resisting Adversarial Attacks. CANDAR 2020: 221-227 - [c67]Van-Tinh Nguyen, Tieu-Khanh Luong, Renyuan Zhang, Yasuhiko Nakashima:
A Compact and Accuracy-Reconfigurable Univariate RBF Kernel Based on Stochastic Logic. ISCAS 2020: 1-5 - [c66]Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima:
A Multi-grained Reconfigurable Accelerator for Approximate Computing. ISVLSI 2020: 90-95 - [c65]Man Wu, Yan Chen, Yirong Kan, Takeshi Nomura, Renyuan Zhang, Yasuhiko Nakashima:
An Elastic Neural Network Toward Multi-Grained Re-configurable Accelerator. NEWCAS 2020: 218-221 - [c64]Renyuan Zhang, Tati Erlina, Tinh Van Nguyen, Yasuhiko Nakashima:
Hybrid Stochastic Computing Circuits in Continuous Statistics Domain. SoCC 2020: 225-230
2010 – 2019
- 2019
- [j22]Yan Chen, Jing Zhang, Yuebing Xu, Yingjie Zhang, Renyuan Zhang, Yasuhiko Nakashima:
An efficient ReRAM-based inference accelerator for convolutional neural networks via activation reuse. IEICE Electron. Express 16(18): 20190396 (2019) - [j21]Yan Chen, Jing Zhang, Yuebing Xu, Yingjie Zhang, Renyuan Zhang, Yasuhiko Nakashima:
A ReRAM-Based Row-Column-Oriented Memory Architecture for Convolutional Neural Networks. IEICE Trans. Electron. 102-C(7): 580-584 (2019) - [j20]Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima:
Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 878-885 (2019) - [c63]Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach. APCC 2019: 496-501 - [c62]Tati Erlina, Yan Chen, Renyuan Zhang, Yasuhiko Nakashima:
An Efficient Time-based Stochastic Computing Circuitry Employing Neuron-MOS. ACM Great Lakes Symposium on VLSI 2019: 51-56 - [c61]Jun Iwamoto, Renyuan Zhang, Yasuhiko Nakashima:
Evaluation of a Chained Systolic Array with High-Speed Links. CANDAR Workshops 2019: 71-77 - [c60]Van Tinh Nguyen, Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima:
A Programmable Approximate Calculation Unit Employing Time-Encoded Stochastic Computing Elements. CANDAR Workshops 2019: 91-96 - [c59]Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima:
GPGPU Implementation of Variational Bayesian Gaussian Mixture Models. CANDAR 2019: 185-190 - [c58]Van-Cam Nguyen, Hoai-Luan Pham, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima:
Digitizing Invoice and Managing VAT Payment Using Blockchain Smart Contract. IEEE ICBC 2019: 74-77 - [c57]Dai Long Hoang, Thi Hong Tran, Yasuhiko Nakashima:
Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah. ICCBN 2019: 17-21 - [c56]Mutsumi Kimura, Kenta Umeda, Keisuke Ikushima, Toshimasa Hori, Ryo Tanaka, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima:
Neuro-inspired System with Crossbar Array of Amorphous Metal-Oxide-Semiconductor Thin-Film Devices as Self-plastic Synapse Units. ICONIP (2) 2019: 481-491 - [c55]Hiroya Ikeda, Hiroki Yamane, Mutsumi Kimura, Yuki Shibayama, Yasuhiko Nakashima:
Evaluation of Neuromorphic Hardware using Cellular Neural Networks and Oxide Semiconductors. IPDPS Workshops 2019: 603-608 - [c54]Yan Chen, Jing Zhang, Yingjie Zhang, Renyuan Zhang, Mutsumi Kimura, Yasuhiko Nakashima:
A Programmable Calculation Unit Employing Memcapacitor-based Neuromorphic Circuit. NEWCAS 2019: 1-4 - [c53]Renyuan Zhang, Yan Chen, Takashi Nakada, Yasuhiko Nakashima:
DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon. SoCC 2019: 132-137 - [i4]Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Yasuhiko Nakashima:
Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems. CoRR abs/1904.00832 (2019) - 2018
- [j19]Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima:
A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. IEICE Trans. Inf. Syst. 101-D(2): 288-302 (2018) - [j18]Dinh-Dung Le, Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(12): 2210-2212 (2018) - [j17]Renyuan Zhang, Noriyuki Uetake, Takashi Nakada, Yasuhiko Nakashima:
Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing. IEEE Micro 38(6): 73-82 (2018) - [c52]Hoang Gia Vu, Takashi Nakada, Yasuhiko Nakashima:
Efficient Multitasking on FPGA Using HDL-Based Checkpointing. ARC 2018: 590-602 - [c51]Takahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima:
EMAXVR: A programmable accelerator employing near ALU utilization to DSA. COOL CHIPS 2018: 1-3 - [c50]Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima:
A programmable analog calculation unit for vector computations. COOL CHIPS 2018: 1-3 - [c49]Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima:
A Secure Remote Healthcare System for Hospital Using Blockchain Smart Contract. GLOBECOM Workshops 2018: 1-6 - [c48]Hiroya Ikeda, Hiroki Yamane, Yuki Shibayama, Mutsumi Kimura, Yasuhiko Nakashima:
Evaluation of Letter Reproduction System Using Cellular Neural Network and Oxide Semiconductor Synapses by Logic Simulation. CANDAR Workshops 2018: 552-554 - [c47]Mutsumi Kimura, Kenta Umeda, Keisuke Ikushima, Toshimasa Hori, Ryo Tanaka, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima:
Hopfield Neural Network with Double-Layer Amorphous Metal-Oxide Semiconductor Thin-Film Devices as Crosspoint-Type Synapse Elements and Working Confirmation of Letter Recognition. ICONIP (7) 2018: 637-646 - [i3]Duc Phuc Nguyen, Dinh-Dung Le, Thi Hong Tran, Huu-Thuan Huynh, Yasuhiko Nakashima:
Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver. CoRR abs/1805.00359 (2018) - 2017
- [j16]Mutsumi Kimura, Ryohei Morita, Sumio Sugisaki, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima:
Cellular neural network formed by simplified processing elements composed of thin-film transistors. Neurocomputing 248: 112-119 (2017) - [j15]Duc Phuc Nguyen, Thi Hong Tran, Yasuhiko Nakashima:
A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes. J. Commun. 12(2): 130-136 (2017) - [c46]Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima:
CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. FCCM 2017: 192 - [c45]Takamasa Mitani, Hisakazu Fukuoka, Yuria Hiraga, Takashi Nakada, Yasuhiko Nakashima:
Compression and Aggregation for Optimizing Information Transmission in Distributed CNN. CANDAR 2017: 112-118 - [c44]Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima:
A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing. CANDAR 2017: 180-186 - [c43]Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima:
Neuromorphic Hardware Using Simplified Elements and Thin-Film Semiconductor Devices as Synapse Elements - Simulation of Hopfield and Cellular Neural Network -. ICONIP (6) 2017: 769-776 - 2016
- [j14]Yasuhiko Nakashima:
Foreword. IEICE Trans. Inf. Syst. 99-D(12): 2858-2859 (2016) - [j13]Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
Performance Optimization of Light-Field Applications on GPU. IEICE Trans. Inf. Syst. 99-D(12): 3072-3081 (2016) - [c42]Hiromasa Kato, Thi Hong Tran, Yasuhiko Nakashima:
ASIC design of a low-complexity K-best Viterbi decoder for IoT applications. APCCAS 2016: 396-399 - [c41]Thi Hong Tran, Soichiro Kanagawa, Duc Phuc Nguyen, Yasuhiko Nakashima:
ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system. COOL Chips 2016: 1-3 - [c40]Hoang Gia Vu, Supasit Kajkamhaeng, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
CPRtree: A Tree-Based Checkpointing Architecture for Heterogeneous FPGA Computing. CANDAR 2016: 57-66 - [c39]Yuttakon Yuttakonkit, Yasuhiko Nakashima:
Performance Comparison of CGRA and Mobile GPU for Light-Field Image Processing. CANDAR 2016: 174-180 - [c38]Masayoshi Fujii, Yuuki Sato, Tomoaki Tsumura, Yasuhiko Nakashima:
Exploiting Bloom Filters for Saving Power Consumption of Auto-Memoization Processor. CANDAR 2016: 354-360 - [c37]Keisuke Fujimoto, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs. CANDAR 2016: 361-367 - [c36]Hiromasa Kato, Satoshi Shimaya, Keisuke Fujimoto, Tomoya Kameda, Thi Hong Tran, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
CPU Meets VR: A Scalable 3D Representation of Manycores for Behavior Analysis. CANDAR 2016: 375-380 - [c35]Mutsumi Kimura, Nao Nakamura, Tomoharu Yokoyama, Tokiyoshi Matsuda, Tomoya Kameda, Yasuhiko Nakashima:
Simplification of Processing Elements in Cellular Neural Networks - Working Confirmation Using Circuit Simulation. ICONIP (2) 2016: 309-317 - [c34]Tomoya Kameda, Mutsumi Kimura, Yasuhiko Nakashima:
Letter Reproduction Simulator for Hardware Design of Cellular Neural Network Using Thin-Film Synapses - Crosspoint-Type Synapses and Simulation Algorithm. ICONIP (2) 2016: 342-350 - 2015
- [j12]Yasuhiko Nakashima:
Foreword. IEICE Trans. Inf. Syst. 98-D(12): 2047 (2015) - [j11]Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. IEICE Trans. Inf. Syst. 98-D(12): 2141-2149 (2015) - [c33]Anna Zhang, Jun Yao, Yasuhiko Nakashima:
Lowering the complexity of k-means clustering by BFS-dijkstra method for graph computing. COOL Chips 2015: 1-3 - [c32]Yuuki Sato, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima:
An Approximate Computing Stack Based on Computation Reuse. CANDAR 2015: 378-384 - [c31]Shohei Takeuchi, Yuttakon Yuttakonkit, Shinya Takamaeda-Yamazaki, Yasuhiko Nakashima:
A Distributed Memory Based Embedded CGRA for Accelerating Stencil Computations. CANDAR 2015: 385-391 - [c30]Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
A CGRA-Based Approach for Accelerating Convolutional Neural Networks. MCSoC 2015: 73-80 - 2014
- [j10]Yukihiro Sasagawa, Jun Yao, Yasuhiko Nakashima:
Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults. IEICE Trans. Inf. Syst. 97-D(12): 3083-3091 (2014) - [j9]Jun Yao, Yasuhiko Nakashima, Naveen Devisetti, Kazuhiro Yoshimura, Takashi Nakada:
A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction. IEICE Trans. Inf. Syst. 97-D(12): 3092-3100 (2014) - [j8]Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka:
A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor. IEEE Micro 34(6): 54-63 (2014) - [c29]Yuko Hara-Azumi, Masaya Kunimoto, Yasuhiko Nakashima:
Emulator-oriented tiny processors for unreliable post-silicon devices: A case study. ASP-DAC 2014: 85-90 - [c28]Jun Yao, Yasuhiko Nakashima, Mitsutoshi Saito, Yohei Hazama, Ryosuke Yamanaka:
A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit. COOL Chips 2014: 1-3 - [c27]Yuttakon Yuttakonkit, Jun Yao, Yasuhiko Nakashima:
A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration. COOL Chips 2014: 1-3 - [c26]Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima:
Better-Than-DMR Techniques for Yield Improvement. FCCM 2014: 34 - [c25]Yoshikazu Inagaki, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima:
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators. CANDAR 2014: 388-393 - [c24]Takanori Tsumura, Yuuki Shibata, Kazutaka Kamimura, Tomoaki Tsumura, Yasuhiko Nakashima:
Hinting for Auto-Memoization Processor Based on Static Binary Analysis. CANDAR 2014: 426-432 - [c23]Yuuki Shibata, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima:
An implementation of Auto-Memoization mechanism on ARM-based superscalar processor. ISSoC 2014: 1-8 - 2013
- [j7]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. IEICE Trans. Inf. Syst. 96-D(1): 1-8 (2013) - [j6]Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima:
Selective Check of Data-Path for Effective Fault Tolerance. IEICE Trans. Inf. Syst. 96-D(8): 1592-1601 (2013) - [c22]Wei Wang, Jun Yao, Youhui Zhang, Wei Xue, Yasuhiko Nakashima, Weimin Zheng:
HW/SW approaches to accelerate GRAPES in an FU array. COOL Chips 2013: 1-3 - [c21]Yuuki Shibata, Kazutaka Kamimura, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima:
CAM Size Reduction Method for Auto-memorization Processor by Considering Characteristics of Loops. CANDAR 2013: 378-384 - 2012
- [j5]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Quantum Walks on the Line with Phase Parameters. IEICE Trans. Inf. Syst. 95-D(3): 722-730 (2012) - [j4]Yukihiro Sasagawa, Jun Yao, Takashi Nakada, Yasuhiko Nakashima:
RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2319-2329 (2012) - [c20]Kazutaka Kamimura, Ryosuke Oda, Tatsuhiro Yamada, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima:
A Speed-up Technique for an Auto-Memoization Processor by Reusing Partial Results of Instruction Regions. ICNC 2012: 49-57 - [c19]Tanvir Ahmed, Jun Yao, Yasuhiko Nakashima:
Introducing OVP awareness to achieve an efficient permanent defect locating. NANOARCH 2012: 43-49 - [c18]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. TAMC 2012: 400-411 - [i2]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. CoRR abs/1202.6444 (2012) - [i1]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. Electron. Colloquium Comput. Complex. TR12 (2012) - 2011
- [j3]Kazuhiro Yoshimura, Takuya Iwakami, Takashi Nakada, Jun Yao, Hajime Shimada, Yasuhiko Nakashima:
An Instruction Mapping Scheme for FU Array Accelerator. IEICE Trans. Inf. Syst. 94-D(2): 286-297 (2011) - [j2]Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
An efficient conversion of quantum circuits to a linear nearest neighbor architecture. Quantum Inf. Comput. 11(1&2): 142-166 (2011) - [c17]Jun Yao, Ryoji Watanabe, Kazuhiro Yoshimura, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima:
An efficient and reliable 1.5-way processor by fusion of space and time redundancies. DSN Workshops 2011: 69-74 - [c16]Ryosuke Oda, Tatsuhiro Yamada, Tomoki Ikegaya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima:
Input Entry Integration for an Auto-Memoization Processor. ICNC 2011: 179-185 - [c15]Naveen Devisetti, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Jun Yao, Yasuhiko Nakashima:
LAPP: A Low Power Array Accelerator with Binary Compatibility. IPDPS Workshops 2011: 854-862 - [c14]Tomoki Ikegaya, Ryosuke Oda, Tatsuhiro Yamada, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima:
A hybrid model of speculative execution and scout threading for auto-memoization processor. SoC 2011: 22-28 - 2010
- [c13]Tomoki Ikegaya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima:
A Speed-Up Technique for an Auto-Memoization Processor by Collectively Reusing Continuous Iterations. ICNC 2010: 63-70 - [c12]Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima:
An Instruction Decomposition Method for Reconfigurable Decoders. IWIA 2010: 39-47 - [c11]Jun Yao, Ryoji Watanabe, Takashi Nakada, Hajime Shimada, Yasuhiko Nakashima, Kazutoshi Kobayashi:
A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. PRDC 2010: 237-238
2000 – 2009
- 2009
- [j1]Yumi Nakajima, Yasuhito Kawano, Hiroshi Sekigawa, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition. Quantum Inf. Comput. 9(5&6): 423-443 (2009) - [c10]Yushi Kamiya, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima:
A Speculative Technique for Auto-Memoization Processor with Multithreading. PDCAT 2009: 160-166 - 2008
- [c9]Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
A Functional Unit with Small Variety of Highly Reliable Cells. PRDC 2008: 353-354 - 2007
- [c8]Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. ARC 2007: 343-349 - [c7]Tomoaki Tsumura, Ikuma Suzuki, Yasuki Ikeuchi, Hiroshi Matsuo, Hiroshi Nakashima, Yasuhiko Nakashima:
Design and evaluation of an auto-memoization processor. Parallel and Distributed Computing and Networks 2007: 230-235 - 2005
- [c6]Jun Yao, Hajime Shimada, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita:
Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption. ISHPC 2005: 494-507 - 2004
- [c5]Kenji Satou, Yasuhiko Nakashima, Shin'ichi Tsuji, Xavier Défago, Akihiko Konagaya:
An Integrated System for Distributed Bioinformatics Environment on Grids. LSGRID 2004: 8-19 - [c4]Alam Mujahid, Koh Kakusho, Michihiko Minoh, Yasuhiko Nakashima, Shin-ichiro Mori, Shinji Tomita:
Simulating realistic force and shape of virtual cloth with adaptive meshes and its parallel implementation in OpenMP. Parallel and Distributed Computing and Networks 2004: 386-391 - [c3]Motohiro Takayama, Yuki Shinomoto, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita:
Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing. PDPTA 2004: 373-382 - 2001
- [c2]Masahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori:
A high-speed dynamic instruction scheduling scheme for superscalar processors. MICRO 2001: 225-236
1990 – 1999
- 1995
- [c1]Yasuhiko Nakashima, Toshiaki Kitamura, Hideo Tamura, Masaaki Takiuchi, Ken'ichi Miura:
Scalar Processor of the VPP500 Parallel Supercomputer. International Conference on Supercomputing 1995: 348-356
Coauthor Index
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