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ORCIDIEEE Design & Test of Computers, Volume 6
Volume 6, Number 1, February 1989
- Brian Leslie, Farid Matta:
Wafer-level testing with a membrane probe. 10-17 - Francois J. Henley:
An ultra high speed test system. 18-24 - Rob Dekker, Frans P. M. Beenker, Loek Thijssen:
Realistic built-in self-test for static RAMs. 26-34 - Clay S. Gloster Jr., Franc Brglez:
Boundary scan with built-in self-test. 36-44 - Eun Sei Park, M. Ray Mercer, Thomas W. Williams:
A statistical model for delay-fault testing. 45-55 - Laurence E. Bays, Chin-Fu Chen, Evelyn M. Fields, Renato N. Gadenz, W. Patrick Hays, Howard S. Moscovitz, Thomas G. Szymanski:
Post-layout verification of the WE DSP32 digital signal processor. 56-66
Volume 6, Number 2, April 1989
- Viktors Berstis:
The V compiler: automating hardware design. 8-17 - Francky Catthoor, Jos van Sas, Luc Inzé, Hugo De Man:
A testability strategy for multiprocessor architecture. 18-34 - Albert E. Casavant, Manuel A. d'Abreu, Martin Dragomirecky, David A. Duff, Jeffrey R. Jasica, Michael J. Hartman, Ki Soo Hwang, William D. Smith:
A synthesis environment for designing DSP systems. 35-44
Volume 6, Number 3, June 1989
- M. Dannie Durand:
Parallel simulated annealing: accuracy vs. speed in placement. 8-34 - William T. Lee:
Engineering a device for electron-beam probing. 36-42 - Shigehiro Funatsu, Masato Kawai, Akihiko Yamada:
Scan design at NEC. 50-51 - Nagesh Vasanthavada, Nick Kanopoulos:
A built-in test module for fault isolation. 58-65
Volume 6, Number 4, August 1989
- Kenneth P. Parker:
The impact of boundary scan on board test. 18-30 - Bulent I. Dervisoglu:
Scan-path architecture for pseudorandom testing. 32-48 - John A. Waicukauski, Eric Lindbloom:
Failure diagnosis of structured VLSI. 49-60
Volume 6, Number 5, October 1989
- Sudipta Bhawmik, Parimal Palchaudhuri:
DFT Expert: designing testable VLSI circuits. 8-19 - Yue-Sun Kuo, S.-Y. Hwang, H. F. Hu:
A data structure for fast region searches. 20-28 - Young-Uk Yu:
VLSI design and CAD technology in Korea. 29-39 - Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada:
Logic simulation engines in Japan. 40-49 - Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar:
Ideas: a tool for VLSI CAD. 50-57 - Sheldon B. Akers Jr., Balakrishnan Krishnamurthy:
Test counting: a tool for VLSI testing. 58-77
Volume 6, Number 6, December 1989
- Patrick Groeneveld:
Wire ordering for detailed routing. 6-17 - Pierre G. Paulin, John P. Knight:
Algorithms for high-level synthesis. 18-31 - Larry Soulé, Anoop Gupta:
Parallel distributed-time logic simulation. 32-48
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