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2020 – today
- 2023
[j24]Anshul Kumar
, Madhu Jain:
Cost Optimization of an Unreliable server queue with two stage service process under hybrid vacation policy. Math. Comput. Simul. 204: 259-281 (2023)- [j23]Anshul Kumar, Ankit Kumar Jain:
A survey on emotion-cause extraction in psychological text using deep learning methods. Prog. Artif. Intell. 12(4): 303-321 (2023) - 2022
- [j22]Saurabh Tewari, Anshul Kumar, Kolin Paul:
Minimizing Off-Chip Memory Access for CNN Accelerators. IEEE Consumer Electron. Mag. 11(3): 95-104 (2022) - [j21]Madhu Jain, Anshul Kumar:
Effect of disaster and balking on M/M/1 driven fluid queue with working vacation. Int. J. Math. Oper. Res. 23(3): 359-371 (2022) - [j20]Anshul Kumar, Ankit Kumar Jain:
Emotion detection in psychological texts by fine-tuning BERT using emotion-cause pair extraction. Int. J. Speech Technol. 25(3): 727-743 (2022) - [j19]Diksha Moolchandani, Anshul Kumar, Smruti R. Sarangi:
Performance and Power Prediction for Concurrent Execution on GPUs. ACM Trans. Archit. Code Optim. 19(3): 35:1-35:27 (2022) - [j18]Diksha Moolchandani, Kishore Yadav, Geesara Kulathunga, Ilya Afanasyev, Anshul Kumar, Manuel Mazzara, Smruti Sarangi:
Game Theory-Based Parameter Tuning for Energy-Efficient Path Planning on Modern UAVs. ACM Trans. Cyber Phys. Syst. 6(4): 34:1-34:29 (2022) - [c77]Saurabh Tewari, Anshul Kumar, Kolin Paul:
SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators. DATE 2022: 580-583 - [c76]Diksha Moolchandani, Nivedita Shrivastava, Anshul Kumar, Smruti R. Sarangi:
PredStereo: An Accurate Real-time Stereo Vision System. WACV 2022: 4078-4087 - 2021
- [j17]Diksha Moolchandani, Anshul Kumar, Smruti R. Sarangi:
Accelerating CNN Inference on ASICs: A Survey. J. Syst. Archit. 113: 101887 (2021) - [j16]Solomon Abera, M. Balakrishnan, Anshul Kumar:
Performance-Energy Trade-off in Modern CMPs. ACM Trans. Archit. Code Optim. 18(1): 3:1-3:26 (2021) - [c75]Diksha Moolchandani, Geesara Prathap, Ilya Afanasyev, Anshul Kumar, Manuel Mazzara, Smruti R. Sarangi:
Game Theory-Based Parameter-Tuning for Path Planning of UAVs. VLSID 2021: 187-192 - [i1]Anshul Kumar, Roger Edwards, Lisa Walker:
The application of predictive analytics to identify at-risk students in health professions education. CoRR abs/2108.07709 (2021) - 2020
- [j15]Diksha Moolchandani, Anshul Kumar, José F. Martínez, Smruti R. Sarangi:
VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 4252-4265 (2020) - [c74]Diksha Moolchandani, Sudhanshu Gupta, Anshul Kumar, Smruti R. Sarangi:
Performance Prediction for Multi-Application Concurrency on GPUs. ISPASS 2020: 306-315 - [c73]Saurabh Tewari, Anshul Kumar, Kolin Paul:
Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators. ISVLSI 2020: 240-245
2010 – 2019
- 2019
- [c72]Solomon Abera Bekele, M. Balakrishnan, Anshul Kumar:
ML Guided Energy-Performance Trade-Off Estimation For Uncore Frequency Scaling. SpringSim 2019: 1-12 - 2018
- [c71]Solomon Abera, M. Balakrishnan, Anshul Kumar:
Performance-Energy Trade-off in CMPs with Per-Core DVFS. ARCS 2018: 225-238 - 2017
- [c70]Solomon Abera, M. Balakrishnan, Anshul Kumar:
PLSS: A Scheduler for Multi-core Embedded Systems. ARCS 2017: 164-176 - 2016
- [c69]Surya Piplani, G. S. Visweswaran, Anshul Kumar:
Impact of crosstalk and process variation on capture power reduction for at-speed test. VTS 2016: 1-6 - 2014
- [j14]Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda:
Shared-port register file architecture for low-energy VLIW processors. ACM Trans. Archit. Code Optim. 11(1): 1:1-1:32 (2014) - 2013
- [c68]U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar:
High performance 3D-FFT implementation. ISCAS 2013: 2227-2230 - 2012
- [j13]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda:
Exploiting UML based validation for compliance checking of TLM 2 based models. Des. Autom. Embed. Syst. 16(2): 93-113 (2012) - 2011
- [c67]Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar:
Exploiting temporal decoupling to accelerate trace-driven NoC emulation. CODES+ISSS 2011: 315-324 - [c66]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda:
A SysML Profile for Development and Early Validation of TLM 2.0 Models. ECMFA 2011: 299-311 - [c65]Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda:
A UML based framework for efficient validation of TLM 2 models. FDL 2011: 1-8 - [c64]Pragun Goyal, Vinay J. Ribeiro, Huzur Saran, Anshul Kumar:
Strap-down Pedestrian Dead-Reckoning system. IPIN 2011: 1-7 - 2010
- [c63]Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul:
A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712 - [c62]Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar:
FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation. CODES+ISSS 2010: 247-256 - [c61]Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar:
Instruction Selection in ASIP Synthesis Using Functional Matching. VLSI Design 2010: 146-151 - [c60]Anshul Kumar, Preeti Ranjan Panda:
Front-End Design Flows for Systems on Chip: An Embedded Tutorial. VLSI Design 2010: 417-422
2000 – 2009
- 2009
- [c59]Awadhesh Kumar Singh, Rohit Bhat, Anshul Kumar:
An Index-Based Mobile Checkpointing and Recovery Algorithm. ICDCN 2009: 200-205 - 2008
- [c58]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors. VLSI Design 2008: 261-266 - [c57]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions. VLSI Design 2008: 348-353 - 2007
- [j12]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. Int. J. Parallel Program. 35(6): 507-527 (2007) - [j11]Anup Gangwar, M. Balakrishnan, Anshul Kumar:
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. ACM Trans. Design Autom. Electr. Syst. 12(1): 1:1-1:29 (2007) - [c56]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Recurring Pattern Identification and its Application to Instruction Set Extension. CDES 2007: 67-73 - [c55]Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda:
Power Reduction in VLIW Processor with Compiler Driven Bypass Network. VLSI Design 2007: 233-238 - [c54]Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Application Specific Datapath Extension with Distributed I/O Functional Units. VLSI Design 2007: 551-558 - 2006
- [c53]Venkat Rao, Nicolas Navet, Gaurav Singhal, Anshul Kumar, G. S. Visweswaran:
Battery aware dynamic scheduling for periodic task graphs. IPDPS 2006 - [c52]Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar:
Rapid Resource-Constrained Hardware Performance Estimation. IEEE International Workshop on Rapid System Prototyping 2006: 40-46 - 2005
- [c51]Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar:
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE 2005: 730-735 - [c50]Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas Navet:
Battery Model for Embedded Systems. VLSI Design 2005: 105-110 - [c49]Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
Integrated On-Chip Storage Evaluation in ASIP Synthesis. VLSI Design 2005: 274-279 - 2004
- [j10]Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
An efficient technique for exploring register file size in ASIP design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1693-1699 (2004) - [c48]Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan:
Automatic synthesis of system on chip multiprocessor architectures for process networks. CODES+ISSS 2004: 60-65 - [c47]Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne:
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. SCOPES 2004: 17-32 - [c46]Venkat Rao, Gaurav Singhal, Anshul Kumar:
Real Time Dynamic Voltage Scaling For Embedded Systems. VLSI Design 2004: 650-653 - [c45]Sourabh Saluja, Anshul Kumar:
Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture. VLSI Design 2004: 761-764 - [c44]Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan:
Synthesis of Application Specific Multiprocessor Architectures for Process Networks. VLSI Design 2004: 780-783 - 2003
- [j9]Sushil Chandra Jain, Anshul Kumar, Shashi Kumar:
Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing. Des. Autom. Embed. Syst. 8(4): 309-326 (2003) - [c43]Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
Exploring Storage Organization in ASIP Synthesis. DSD 2003: 120-127 - [c42]Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar:
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. VLSI Design 2003: 177-182 - [c41]Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar:
SoC Synthesis with Automatic Hardware Software Interface Generation. VLSI Design 2003: 585- - 2002
- [c40]Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
An efficient technique for exploring register file size in ASIP synthesis. CASES 2002: 252-261 - [c39]Sushil Chandra Jain, Anshul Kumar, Shashi Kumar:
Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards. FPT 2002: 298-301 - [c38]M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha:
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7 - [c37]M. Balakrishnan, Anshul Kumar, C. P. Joshi:
A New Performance Evaluation Approach for System Level Design Space Exploration. ISSS 2002: 180-185 - [c36]Sushil Chandra Jain, Anshul Kumar, Shashi Kumar:
Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing. IEEE International Workshop on Rapid System Prototyping 2002: 66- - [c35]Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar:
Exploring the Number of Register Windows in ASIP Synthesis. ASP-DAC/VLSI Design 2002: 233-238 - [c34]Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan:
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. ASP-DAC/VLSI Design 2002: 535-540 - 2001
- [c33]Anupam Rastogi, M. Balakrishnan, Anshul Kumar:
Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. VLSI Design 2001: 23-28 - [c32]Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
ASIP Design Methodologies : Survey and Issues. VLSI Design 2001: 76- - [c31]Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busá:
Synthesizing A Long Latency Unit Within Vliw Processor. VLSI Design 2001: 460- - 2000
- [j8]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMS. J. Syst. Archit. 46(2): 181-199 (2000) - [j7]Johnny Öberg, Anshul Kumar, Ahmed Hemani:
Grammar-based hardware synthesis from port-size independent specifications. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 184-194 (2000) - [c30]Sushil Chandra Jain, Anshul Kumar, Shashi Kumar:
Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards. FPL 2000: 201-210 - [c29]Arvind Rajawat, M. Balakrishnan, Anshul Kumar:
nterface Synthesis: Issues and Approaches. VLSI Design 2000: 92 - [c28]Sushil Chandra Jain, Shashi Kumar, Anshul Kumar:
Evaluation of Various Routing Architectures for Multi-FPGA Boards. VLSI Design 2000: 262-267
1990 – 1999
- 1999
- [j6]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Built-in Self Test Based on Multiple On-Chip Signature Checking. J. Electron. Test. 14(3): 227-244 (1999) - 1998
- [j5]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. J. Electron. Test. 12(3): 199-216 (1998) - [j4]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Direct mapping of RTL structures onto LUT-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(7): 624-631 (1998) - [c27]Johnny Öberg, Ahmed Hemani, Anshul Kumar:
Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. DATE 1998: 596-603 - [c26]Johnny Öberg, Anshul Kumar, Ahmed Hemani:
Specification of Exception Handling in Grammar-Based Hardware Synthesis. EUROMICRO 1998: 10038-10041 - [c25]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Hybrid Testing Schemes Based on Mutual and Signature Testing. VLSI Design 1998: 293- - [c24]Johnny Öberg, Axel Jantsch, Anshul Kumar:
An Object-Oriented Concept for Intelligent Library Functions. VLSI Design 1998: 355-358 - [c23]Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar:
Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. VLSI Design 1998: 400-405 - [c22]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
On-Chip Signature Checking for Embedded Memories. VLSI Design 1998: 558-563 - 1997
- [c21]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMs. ED&TC 1997: 625 - [c20]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Optimal Clock Period for Synthesized Data Paths. VLSI Design 1997: 134-139 - [c19]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Efficient Implementation of Multiple On-Chip Signature Checking. VLSI Design 1997: 297-302 - 1996
- [c18]Johnny Öberg, Anshul Kumar, Ahmed Hemani:
Grammar-Based Hardware Synthesis of Data Communication Protocols. ISSS 1996: 14-19 - [c17]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A Novel BIST Architecture With Built-in Self Check. VLSI Design 1996: 57-60 - [c16]Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar:
A multiplier generator for Xilinx FPGAs. VLSI Design 1996: 322-323 - 1995
- [c15]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. FPL 1995: 139-148 - [c14]Gurmeet Singh Manku, Anshul Kumar, Shashi Kumar:
Circuit partitioning with partial order for mixed simulation emulation environment. RSP 1995: 201-209 - [c13]Alok Kumar, Anshul Kumar, M. Balakrishnan:
Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. VLSI Design 1995: 75-80 - [c12]B. M. Subraya, Anshul Kumar, Shashi Kumar:
An HOL based framework for design of correct high level synthesizers. VLSI Design 1995: 249-254 - 1994
- [c11]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
An Efficient Technique for Mapping RTL Structures onto FPGAs. FPL 1994: 99-110 - [c10]A. R. Naseer, M. Balakrishnan, Anshul Kumar:
FAST: FPGA Targeted RTL Structure Synthesis Technique. VLSI Design 1994: 21-24 - 1993
- [c9]C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer:
High Level Design Experiences with IDEAS. VLSI Design 1993: 110 - [c8]M. V. Rao, M. Balakrishnan, Anshul Kumar:
DESSERT: Design Space Exploration of RT Level Components. VLSI Design 1993: 299-304 - 1992
- [c7]Manu Lauria, Shashi Kumar, Anshul Kumar:
A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas. VLSI Design 1992: 181-186 - [c6]Prashant P. Nedungadi, M. Balakrishnan, Anshul Kumar:
Data Path Synthesis With Global Time Constraint. VLSI Design 1992: 322-323
1980 – 1989
- 1989
- [j3]Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar:
Ideas: a tool for VLSI CAD. IEEE Des. Test 6(5): 50-57 (1989) - [c5]Anshul Kumar, Shashi Kumar, P. Kulshreshtha, Sudipto Ghose:
Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions. DAC 1989: 147-154 - 1986
- [j2]Anshul Kumar, Anjali Arya, V. V. Swaminathan, Amit Misra:
Automatic Generation of Digital System Schematic Diagrams. IEEE Des. Test 3(1): 58-65 (1986) - 1985
- [c4]Kumar Ramayya, Anshul Kumar, Surendra Prasad:
An automated data path synthesizer for a canonic structure, implementable in VLSI. DAC 1985: 381-387 - [c3]Anjali Arya, Anshul Kumar, V. V. Swaminathan, Amit Misra:
Automatic generation of digital system schematic diagrams. DAC 1985: 388-395 - 1984
- [c2]Anshul Kumar, George A. Bekey:
Recognition of consonants using an ARMA model of the speech signal. ICASSP 1984: 292-295 - 1983
- [j1]Melvin A. Breuer, Anshul Kumar:
A methodology for custom VLSI layout. IEEE Trans. Syst. Man Cybern. 13(4): 470-476 (1983) - 1980
- [c1]Anshul Kumar, P. C. P. Bhatt:
A Structured Language for CAD of Digital Systems. ISCA 1980: 308-316
Coauthor Index
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