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2020 – today
- 2024
[i6]Issa Saba, Eishi Arima, Dai Liu, Martin Schulz
:
Orchestrated Co-scheduling, Resource Partitioning, and Power Capping on CPU-GPU Heterogeneous Systems via Machine Learning. CoRR abs/2405.03831 (2024)- [i5]Eishi Arima, Minjoon Kang, Issa Saba, Josef Weidendorfer, Carsten Trinitis, Martin Schulz:
Optimizing Hardware Resource Partitioning and Job Allocations on Modern GPUs under Power Caps. CoRR abs/2405.03838 (2024) - [i4]Eishi Arima, Isaías A. Comprés, Martin Schulz:
On the Convergence of Malleability and the HPC PowerStack: Exploiting Dynamism in Over-Provisioned and Power-Constrained HPC Systems. CoRR abs/2405.03847 (2024) - [i3]Urvij Saroliya, Eishi Arima, Dai Liu, Martin Schulz:
Hierarchical Resource Partitioning on Modern GPUs: A Reinforcement Learning Approach. CoRR abs/2405.08754 (2024) - 2023
- [c15]Urvij Saroliya, Eishi Arima, Dai Liu, Martin Schulz:
Hierarchical Resource Partitioning on Modern GPUs: A Reinforcement Learning Approach. CLUSTER 2023: 185-196 - [c14]Mohak Chadha, Eishi Arima, Amir Raoofy, Michael Gerndt, Martin Schulz:
Sustainability in HPC: Vision and Opportunities. SC Workshops 2023: 1876-1880 - [c13]Isaías Comprés, Eishi Arima, Martin Schulz, Tiberiu Rotaru, Rui Machado:
Probabilistic Job History Conversion and Performance Model Generation for Malleable Scheduling Simulations. ISC Workshops 2023: 82-94 - [c12]Mohak Chadha, Thandayuthapani Subramanian, Eishi Arima, Michael Gerndt, Martin Schulz, Osama Abboud:
GreenCourier: Carbon-Aware Scheduling for Serverless Functions. WOSC@Middleware 2023: 18-23 - [i2]Mohak Chadha, Eishi Arima, Amir Raoofy, Michael Gerndt, Martin Schulz:
Sustainability in HPC: Vision and Opportunities. CoRR abs/2309.13473 (2023) - [i1]Mohak Chadha, Thandayuthapani Subramanian, Eishi Arima, Michael Gerndt, Martin Schulz, Osama Abboud:
GreenCourier: Carbon-Aware Scheduling for Serverless Functions. CoRR abs/2310.20375 (2023) - 2022
- [c11]Issa Saba, Eishi Arima, Dai Liu, Martin Schulz:
Orchestrated Co-scheduling, Resource Partitioning, and Power Capping on CPU-GPU Heterogeneous Systems via Machine Learning. ARCS 2022: 51-67 - [c10]Eishi Arima, Minjoon Kang, Issa Saba, Josef Weidendorfer, Carsten Trinitis, Martin Schulz:
Optimizing Hardware Resource Partitioning and Job Allocations on Modern GPUs under Power Caps. ICPP Workshops 2022: 9:1-9:10 - [c9]Eishi Arima, Isaías Comprés, Martin Schulz:
On the Convergence of Malleability and the HPC PowerStack: Exploiting Dynamism in Over-Provisioned and Power-Constrained HPC Systems. ISC Workshops 2022: 206-217 - 2021
- [c8]Eishi Arima, Yuetsu Kodama, Tetsuya Odajima, Miwako Tsuji, Mitsuhisa Sato:
Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip. COOL CHIPS 2021: 1-6 - 2020
- [c7]Yuetsu Kodama, Tetsuya Odajima, Eishi Arima, Mitsuhisa Sato:
Evaluation of Power Management Control on the Supercomputer Fugaku. CLUSTER 2020: 484-493 - [c6]Eishi Arima:
Classification-Based Unified Cache Replacement via Partitioned Victim Address History. DSD 2020: 101-108 - [c5]Eishi Arima, Toshihiro Hanawa, Carsten Trinitis, Martin Schulz:
Footprint-Aware Power Capping for Hybrid Memory Based Systems. ISC 2020: 347-369 - [c4]Eishi Arima, Martin Schulz:
Pattern-Aware Staging for Hybrid Memory Systems. ISC 2020: 474-495 - [e1]Maurizio Palesi, Gianluca Palermo, Catherine Graves, Eishi Arima:
Proceedings of the 17th ACM International Conference on Computing Frontiers, CF 2020, Catania, Sicily, Italy, May 11-13, 2020. ACM 2020, ISBN 978-1-4503-7956-4 [contents]
2010 – 2019
- 2016
- [c3]Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC 2016: 132-133 - 2015
- [c2]Eishi Arima, Hiroki Noguchi, Takashi Nakada, Shinobu Miwa, Susumu Takeda, Shinobu Fujita, Hiroshi Nakamura:
Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. ICCD 2015: 149-156 - 2013
- [c1]Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura:
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE 2013: 1813-1818
Coauthor Index
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last updated on 2024-08-05 20:22 CEST by the dblp team
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