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ORCIDVishnu Balan
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2020 – today
- 2023
[c7]Ying Wei, Yi Chieh Huang, Haiming Tang, Nithya Sankaran, Ish Chadha, Dai Dai, Olakanmi Oluwole, Vishnu Balan, Edward Lee:
NVLink-C2C: A Coherent Off Package Chip-to-Chip Interconnect with 40Gbps/pin Single-ended Signaling. ISSCC 2023: 160-161- 2021
- [c6]Jack Choquette, Ming-Ju Edward Lee, Ronny Krashinsky, Vishnu Balan, Brucek Khailany:
3.2 The A100 Datacenter GPU and Ampere Architecture. ISSCC 2021: 48-50
2010 – 2019
- 2014
- [j4]Vishnu Balan, Olakanmi Oluwole, Gregory Kodani, Charlie Zhong, Ratnakar Dadi, Arif Amin, Ahmed Ragab, Ming-Ju Edward Lee:
A 15-22 Gbps Serial Link in 28 nm CMOS With Direct DFE. IEEE J. Solid State Circuits 49(12): 3104-3115 (2014) - [c5]Vishnu Balan, Olakanmi Oluwole, Gregory Kodani, Charlie Zhong, Sanjeev Maheswari, Ratnakar Dadi, Arif Amin, Gautam Bhatia, Peter Mills, Ahmed Ragab, Ming-Ju Edward Lee:
26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS. ISSCC 2014: 438-439
2000 – 2009
- 2008
- [c4]Sandeep Gupta, José Tellado, Sridhar Begur, Frank Yang, Vishnu Balan, Michael A. Inerfield, Dariush Dabiri, John Dring, Sachin Goel, Kumaraguru Muthukumaraswamy, Frank McCarthy, Glenn Golden, Jiangfeng Wu, Susan Arno, Sanjay Kasturia:
A 10Gb/s IEEE 802.3an-Compliant Ethernet Transceiver for 100m UTP Cable in 0.13μm CMOS. ISSCC 2008: 106-107 - 2005
- [j3]Vishnu Balan, Joe Caroselli, Jenn-Gang Chern, Catherine Chow, Ratnakar Dadi, Chintan Desai, Leo Fang, David Hsu, Pankaj Joshi, Hiroshi Kimura, Cathy Ye Liu, Tzu-Wang Pan, Ryan Park, Cindy You, Yi Zeng, Eric Zhang, Freeman Zhong:
A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization. IEEE J. Solid State Circuits 40(9): 1957-1967 (2005) - 2004
- [c3]Vishnu Balan, Joe Caroselli, Jenn-Gang Chern, Chintan Desai, Cathy Liu:
A 4.8-6.4 Gbps serial link for back-plane applications using decision feedback equalization. CICC 2004: 31-34 - 2003
- [j2]Vishnu Balan:
A low-voltage regulator circuit with self-bias to improve accuracy. IEEE J. Solid State Circuits 38(2): 365-368 (2003) - 2002
- [c2]Vishnu Balan, Tzuwang Pan:
A crystal oscillator with automatic amplitude control and digitally controlled pulling range of +-100 ppm. ISCAS (5) 2002: 461-464
1990 – 1999
- 1999
- [j1]Narendra Rao, Vishnu Balan, R. Contreras:
A 3-V, 10-100-MHz continuous-time seventh-order 0.05° equiripple linear phase filter. IEEE J. Solid State Circuits 34(11): 1676-1682 (1999) - [c1]Narendra Rao, Vishnu Balan, Richard Contreras, Jenn-Gang Chern, Y. Wang:
A 150 MHz continuous-time seventh order 0.05° equiripple linear phase filter. ISCAS (2) 1999: 664-666
Coauthor Index
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