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2020 – today
- 2022
[j2]Kent Edrian Lozada
, Il-Hoon Jang, Gyeom-Je Bae, Dong-Hun Lee, Ye-Dam Kim, Hankyu Lee, Seong Joong Kim, Seung-Tak Ryu:
A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3635-3639 (2022)- 2021
- [c3]Seung-Yeob Baek, Il-Hoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim, Youngjae Cho, Jongshin Shin:
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. ISSCC 2021: 172-174
2010 – 2019
- 2018
- [j1]Il-Hoon Jang, Min-Jae Seo, Sang-Hyun Cho, Jae-Keun Lee, Seung-Yeob Baek, Sunwoo Kwon, Michael Choi, Hyung-Jong Ko, Seung-Tak Ryu:
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. IEEE J. Solid State Circuits 53(4): 1139-1148 (2018) - 2017
- [c2]Ki-Hoon Seo, Il-Hoon Jang, Kyung-Jun Noh, Seung-Tak Ryu:
An incremental zoom sturdy MASH ADC. MWSCAS 2017: 1013-1016 - 2015
- [c1]Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu:
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. ISSCC 2015: 1-3
Coauthor Index
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