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ORCIDPranav Ashar
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2010 – 2019
- 2019
[c52]Pranav Ashar, Vinod Viswanath
:
Closing the Verification Gap with Static Sign-off. ISQED 2019: 343-347- 2017
- [c51]Pranav Ashar, Vikas Sachdeva, Vinod Viswanath:
Failures and verification solutions related to untimed paths in SOCs. ISQED 2017: 460-465 - 2016
- [c50]Pranav Ashar:
A paradigm shift in verification methodology. FMCAD 2016: 6 - 2013
- [c49]Pranav Ashar:
Static verification based signoff - A key enabler for managing verification complexity in the modern soc. FMCAD 2013: 15 - 2010
- [c48]Pranav Ashar:
Clock domain verification challenges and scalable solutions. HLDVT 2010: 66
2000 – 2009
- 2008
- [j18]Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1513-1517 (2008) - [j17]Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient SAT-based bounded model checking for software verification. Theor. Comput. Sci. 404(3): 256-274 (2008) - 2007
- [i1]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Verification of Embedded Memory Systems using Efficient Memory Modeling. CoRR abs/0710.4666 (2007) - 2006
- [j16]Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar:
Efficient distributed SAT and SAT-based distributed Bounded Model Checking. Int. J. Softw. Tools Technol. Transf. 8(4-5): 387-396 (2006) - [c47]Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley:
Panel: Assertion-Based Verification -What's the Big Deal? HLDVT 2006: 183 - 2005
- [c46]Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar:
F-Soft: Software Verification Platform. CAV 2005: 301-306 - [c45]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Beyond safety: customized SAT-based model checking. DAC 2005: 738-743 - [c44]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Verification of Embedded Memory Systems using Efficient Memory Modeling. DATE 2005: 1096-1101 - [c43]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. TACAS 2005: 575-580 - [c42]Aarti Gupta, Malay K. Ganai, Pranav Ashar:
Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. VLSI Design 2005: 183-188 - 2004
- [c41]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient Modeling of Embedded Memories in Bounded Model Checking. CAV 2004: 440-452 - [c40]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. ICCAD 2004: 510-517 - [c39]Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang:
Efficient SAT-based Bounded Model Checking for Software Verification. ISoLA (Preliminary proceedings) 2004: 157-164 - 2003
- [c38]Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar:
Abstraction and BDDs Complement SAT-Based BMC in DiVer. CAV 2003: 206-209 - [c37]Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar:
Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. CHARME 2003: 334-347 - [c36]Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar:
Learning from BDDs in SAT-based bounded model checking. DAC 2003: 824-829 - [c35]Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar:
Iterative Abstraction using SAT-based BMC with Proof Analysis. ICCAD 2003: 416-423 - 2002
- [j15]Farzan Fallah, Pranav Ashar, Srinivas Devadas:
Functional vector generation for sequential HDL models under an observability-based code coverage metric. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 919-923 (2002) - [c34]Srihari Cadambi, Chandra Mulpuri, Pranav Ashar:
A fast, inexpensive and scalable hardware acceleration technique for functional simulation. DAC 2002: 570-575 - [c33]Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik:
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750 - [c32]Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi:
Property-Specific Testbench Generation for Guided Simulation. ASP-DAC/VLSI Design 2002: 524- - 2001
- [j14]Pranav Ashar, Aarti Gupta, Sharad Malik:
Using complete-1-distinguishability for FSM equivalence checking. ACM Trans. Design Autom. Electr. Syst. 6(4): 569-590 (2001) - [c31]Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar:
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. DAC 2001: 536-541 - [c30]Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar:
Property-specific witness graph generation for guided simulation. DATE 2001: 799 - [c29]Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik:
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. ICCAD 2001: 286-292 - 2000
- [j13]Zhen Luo, Margaret Martonosi, Pranav Ashar:
An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking. VLSI Design 10(3): 249-263 (2000) - [c28]Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta:
SAT-Based Image Computation with Application in Reachability Analysis. FMCAD 2000: 354-371 - [c27]Aarti Gupta, Pranav Ashar:
Fast Error Diagnosis for Combinational Verification. VLSI Design 2000: 442-448 - [c26]Yang Xia, Pranav Ashar:
Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. VLSI Design 2000: 449-
1990 – 1999
- 1999
- [j12]Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik:
Using configurable computing to accelerate Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 861-868 (1999) - [c25]Aarti Gupta, Pranav Ashar, Sharad Malik:
Exploiting Retiming in a Guided Simulation Based Validation Methodology. CHARME 1999: 350-353 - [c24]Farzan Fallah, Pranav Ashar, Srinivas Devadas:
Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage. DAC 1999: 666-671 - [c23]Zhen Luo, Margaret Martonosi, Pranav Ashar:
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking. FCCM 1999: 158-167 - [c22]Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya:
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD 1999: 458-466 - 1998
- [j11]Vivek Tiwari, Sharad Malik, Pranav Ashar:
Guarded evaluation: pushing power management to logic synthesis/design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 1051-1060 (1998) - [c21]Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi:
Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. DAC 1998: 194-199 - [c20]Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik:
Accelerating Boolean Satisfiability with Configurable Hardware. FCCM 1998: 186-195 - [c19]Peixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik:
Solving Boolean Satisfiability with Dynamic Hardware Configurations. FPL 1998: 326-335 - [c18]Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama:
Verification of RTL generated from scheduled behavior in a high-level synthesis flow. ICCAD 1998: 517-524 - [c17]Aarti Gupta, Pranav Ashar:
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. VLSI Design 1998: 222-225 - 1997
- [c16]Aarti Gupta, Sharad Malik, Pranav Ashar:
Toward Formalizing a Validation Methodology Using Simulation Coverage. DAC 1997: 740-745 - 1996
- [j10]Vivek Tiwari, Pranav Ashar, Sharad Malik:
Technology mapping for low power in logic synthesis. Integr. 20(3): 243-268 (1996) - [c15]José Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar:
Scheduling Techniques to Enable Power Management. DAC 1996: 349-352 - [c14]Pranav Ashar, Aarti Gupta, Sharad Malik:
Using complete-1-distinguishability for FSM equivalence checking. ICCAD 1996: 346-353 - 1995
- [j9]Pranav Ashar, Sharad Malik:
Functional timing analysis using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 1025-1030 (1995) - [j8]Pranav Ashar, Sujit Dey, Sharad Malik:
Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1067-1075 (1995) - [j7]Anand Raghunathan, Pranav Ashar, Sharad Malik:
Test generation for cyclic combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1408-1414 (1995) - [c13]Pranav Ashar, Sharad Malik:
Fast functional simulation using branching programs. ICCAD 1995: 408-412 - [c12]Vivek Tiwari, Sharad Malik, Pranav Ashar:
Guarded evaluation: pushing power management to logic synthesis/design. ISLPD 1995: 221-226 - [c11]Anand Raghunathan, Pranav Ashar, Sharad Malik:
Test generation for cyclic combinational circuits. VLSI Design 1995: 104-109 - 1994
- [c10]Pranav Ashar, Sharad Malik:
Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. DAC 1994: 77-80 - [c9]Pranav Ashar, Matthew Cheong:
Efficient breadth-first manipulation of binary decision diagrams. ICCAD 1994: 622-627 - 1993
- [j6]Pranav Ashar, Srinivas Devadas, Kurt Keutzer:
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. Formal Methods Syst. Des. 2(1): 93-112 (1993) - [j5]Pranav Ashar, Srinivas Devadas, Kurt Keutzer:
Path-delay-fault testability properties of multiplexor-based networks. Integr. 15(1): 1-23 (1993) - [c8]Vivek Tiwari, Pranav Ashar, Sharad Malik:
Technology Mapping for Lower Power. DAC 1993: 74-79 - 1992
- [j4]Pranav Ashar, Abhijit Ghosh, Srinivas Devadas:
Boolean satisfiability and equivalence checking using general Binary Decision Diagrams. Integr. 13(1): 1-16 (1992) - [c7]Pranav Ashar, Sujit Dey, Sharad Malik:
Exploiting multi-cycle false paths in the performance optimization of sequential circuits. ICCAD 1992: 510-517 - 1991
- [j3]Pranav Ashar, Srinivas Devadas, A. Richard Newton:
Optimum and heuristic algorithms for an approach to finite state machine decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(3): 296-310 (1991) - [j2]Pranav Ashar, Srinivas Devadas, A. Richard Newton:
Irredundant interacting sequential machines via optimal logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(3): 311-325 (1991) - [c6]Pranav Ashar, Abhijit Ghosh, Srinivas Devadas:
Boolean Satisfiability and Equivalence Checking Using General Binary Decision Diagrams. ICCD 1991: 259-264 - [c5]Pranav Ashar, Srinivas Devadas, Kurt Keutzer:
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. ITC 1991: 887-896 - 1990
- [c4]Pranav Ashar, Srinivas Devadas, A. Richard Newton:
A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. DAC 1990: 601-606 - [c3]Pranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test. ICCAD 1990: 84-87 - [c2]Pranav Ashar, Srinivas Devadas, A. Richard Newton:
Testability driven synthesis of interacting finite state machines. ICCD 1990: 273-276
1980 – 1989
- 1989
- [c1]Pranav Ashar, Srinivas Devadas, A. Richard Newton:
Optimum and heuristic algorithms for finite state machine decomposition and partitioning. ICCAD 1989: 216-219 - 1988
- [j1]K. Radhakrishna Rao, Pranav Ashar:
Magnitude locked loop. Proc. IEEE 76(2): 201-203 (1988)
Coauthor Index
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