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ORCID27th DAC 1990: Orlando, Florida, USA
- Richard C. Smith:
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990. IEEE Computer Society Press 1990, ISBN 0-89791-363-9
HDL Validation and Intermediate Format
- James Armstrong, Chang Cho, Sandeep Shah, Chakravarthy Kosaraju:
The VHDL Validation Suite. 2-7 - Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima:
NES: The Behavioral Model for the Formal Semantics of a Hardware Design Language UDL/I. 8-13 - Nikil D. Dutt
, Tedd Hadley, Daniel Gajski:
An Intermediate Representation for Behavioral Synthesis. 14-19
Probabilistic Techniques in Placement: Annealing and Its Competitors
- Ralph-Michael Kling, Prithviraj Banerjee:
Optimization by Simulated Evolution with Applications to Standard Cell Placement. 20-25 - Youssef Saab, Vasant B. Rao:
Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems. 26-31 - Michael Upton, Khosrow Samii, Stephen Sugiyama:
Integrated Placement for Mixed Macro Cell and Standard Cell Designs. 32-35 - Abhijit Chatterjee, Richard I. Hartley:
A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing. 36-39
Binary Decision Diagrams - Implementations and Applications
- Karl S. Brace, Richard L. Rudell, Randal E. Bryant:
Efficient Implementation of a BDD Package. 40-45 - Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill:
Sequential Circuit Verification Using Symbolic Model Checking. 46-51 - Shin-ichi Minato, Nagisa Ishiura, Shuzo Yajima:
Shared Binary Decision Diagram with Attributed Edges for Efficient Boolean function Manipulation. 52-57
Panel
- Petra Michel:
Women in the Microelectronics Industry (Panel Abstract). DAC 1990: 58
New Scheduling, Allocation and Mapping Techniques
- David C. Ku, Giovanni De Micheli:
Relative Scheduling Under Timing Constraints. 59-64 - Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
Optimum and Heuristic Data Path Scheduling Under Resource Constraints. 65-70 - Richard J. Cloutier, Donald E. Thomas:
The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm. 71-76 - Christos A. Papachristou, Haluk Konuk:
A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm. 77-83
Timing Driven Layout Techniques
- Wilm E. Donath, Reini J. Norman, Bhuwan K. Agrawal, Stephen E. Bello, Sang-Yong Han, Jerome M. Kurtzberg, Paul Lowy, Roger I. McMillan:
Timing Driven Placement Using Complete Path Delays. 84-89 - Suphachai Sutanthavibul, Eugene Shragowitz:
An Adaptive Timing-Driven Layout for High Speed VLSI. 90-95 - Masayuki Terai, Kazuhiro Takahashi, Koji Sato:
A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint. 96-102 - Ichiang Lin, David Hung-Chang Du:
Performance-Driven Constructive Placement. 103-106 - Daniel R. Brasen, Michael L. Bushnell:
MHERTZ: A New Optimization Algorithm for Floorplanning and Global Routing. 107-110
Timing Verification
- Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun:
Analysis and Design of Latch-Controlled Synchronous Digital Circuits. 111-117 - Alan R. Martello, Steven P. Levitan, Donald M. Chiarulli:
Timing Verification Using HDTV. 118-123 - Patrick C. McGeer, Robert K. Brayton:
Timing Analysis in Precharge/Unate Networks. 124-129 - Nagisa Ishiura, Yutaka Deguchi, Shuzo Yajima:
Coded Time-Symbolic Simulation Using Shared Binary Decision Diagram. 130-135
Data Management and Version Control
- Andrea Casotto, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Design Management Based on Design Traces. 136-141 - Pieter van der Wolf, G. W. Sloof, Peter Bingley, Patrick M. Dewilde:
Meta Data Management in the NELSIS CAD Framework. 142-149 - Gwo-Dong Chen, Daniel Gajski:
An Intelligent Component Database for Behavioral Synthesis. 150-155 - Lung-Chun Liu:
Design Data Management in a CAD Framework Environment. 156-161
Data Path Optimization Algorithms
- Douglas M. Grant, Peter B. Denyer:
Memory, Control and Communications Synthesis for Scheduled Algorithms. 162-167 - Tai A. Ly, W. Lloyd Elwood, Emil F. Girczyc:
A Generalized Interconnect Model for Data Path Synthesis. 168-173 - Kristen N. McNall, Albert E. Casavant:
Automatic Operator Configuration in the Synthesis of Pipelined Architectures. 174-179
Issues in Floorplanning
- Ting-Chi Wang, D. F. Wong:
An Optimal Algorithm for Floorplan Area Optimization. 180-186 - Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen:
An Analytical Approach to Floorplan Design and Optimization. 187-192 - Deborah C. Wang:
Pad Placement and Ring Routing for Custom Chip Layout. 193-199
Formal Methods for Design Verification
- Mike Spreitzer:
Comparing Structurally Different Views of a VLSI Design. 200-212 - Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Verification of Interacting Sequential Circuits. 213-219
Panel
- Basant R. Chawla:
Distributed Computing Environment for Design Automation in the 90's (Panel Abstract). DAC 1990: 220
Synthesis and Testability
- Srinivas Devadas, Kurt Keutzer:
Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. 221-227 - Kurt Keutzer, Sharad Malik, Alexander Saldanha:
Is Redundancy Necessary to Reduce Delay. 228-234 - Vishwani D. Agrawal, Kwang-Ting Cheng:
Test Function Specification in Synthesis. 235-240
Tutorial: Layout Synthesis of MOS Digital Cells
- Antun Domic:
Layout Synthesis of MOS Digital Cells. 241-245
Layout Verification
- Goro Suzuki, Yoshio Okamura:
A Practical Online Design Rule Checking System. 246-252 - Erik C. Carlson, Rob A. Rutenbar:
Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. 253-259 - Bruce A. Tonkin:
Circuit Extraction on a Message-Based Multiprocessor. 260-265
Software Engineering in Design Automation
- Timothy J. Barnes:
SKILL: A CAD System Extension Language. 266-271 - Marwan A. Jabri:
BREL - a Prolog Knowledge-based System Shell for VLSI CAD. 272-277 - Kenneth W. Fiduk, Sally Kleinfeldt, Marta Kosarchyn, Eileen B. Perez:
Design Methodology Management - a CAD Framework Initiative Perspective. 278-283
Boolean Methods
- Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita:
Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. 284-289 - Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Reduced Offsets for Two-Level Multi-Valued Logic Minimization. 290-296 - Hamid Savoj, Robert K. Brayton:
The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. 297-301 - Kwang-Ting Cheng, Vishwani D. Agrawal:
An Entropy Measure for the Complexity of Multi-Output Boolean Functions. 302-305
Layout Synthesis: Cell Assembly
- H. Cai, Stefaan Note, Paul Six, Hugo De Man:
A Data Path Layout Assembler for High Performance DSP Circuits. 306-311 - Dwight D. Hill, Don Shugard:
Global Routing Considerations in a Cell Synthesis System. 312-316 - Dwight D. Hill, Bryan Preas:
Benchmarks for Cell Synthesis. 317-320
Computer Aids For IC Manufacturability
- Tsuneo Okubo, Takashi Watanabe, Kou Wada:
New Algorithm for Overlapping Cell Treatment in Hierarchical CAD Data/Electron Beam Exposure Data Conversion. 321-326 - Chin-Long Wey, Jyhyeung Ding, Tsin-Yuan Chang:
Design of Repairable and Fully Diagnosable Folded PLAs for Yield Enhancement. 327-332 - D. David Forsythe, Atul P. Agarwal, Chune-Sin Yeh, Sheldon Aronowitz, Bhaskar Gadepally:
NASFLOW, a Simulation Tool for Silicon Technology Development. 333-337
Panel
- Alberto L. Sangiovanni-Vincentelli:
Testing Strategies for the 1990's (Panel Abstract). DAC 1990: 338
Timing and Routing Optimization in Synthesis
- Kuang-Chien Chen, Saburo Muroga:
Timing Optimization for Multi-Level Combinational Networks. 339-344 - Naohiro Kageyama, Chihei Miura, Tsuguo Shimizu:
Logic Optimization Algorithm by Linear Programming Approach. 345-348 - Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh:
Delay and Area Optimization in Standard-Cell Design. 349-352 - Pak K. Chan:
Algorithms for Library-Specific Sizing of Combinational Logic. 353-356 - Kanwar Jit Singh, Alberto L. Sangiovanni-Vincentelli:
A Heuristic Algorithm for the Fanout Problem. 357-360 - John P. Fishburn:
A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between. 361-364 - Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot:
Multilevel Synthesis Minimizing the Routing Factor. 365-368
Compactors: Theory and Practice
- Akira Onozawa:
Layout Compaction with Attractive and Repulsive Constraints. 369-374 - David Marple:
A Hierarchy Preserving Hierarchical Compactor. 375-381 - Chi-Yuan Lo, Ravi Varadarajan:
An O(n1.5logn) 1-d Compaction Algorithm. 382-387 - Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori:
Datapath Generator Based on Gate-Level Symbolic Layout. 388-393
Electrical Simulation
- Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh:
Parallel Circuit Simulation Using Hierarchical Relaxation. 394-399 - Gung-Chung Yang:
PARASPICE: A Parallel Circuit Simulator for Shared-Memory Multiprocessors. 400-405 - Steven Paul McCormick, Jonathan Allen:
Waveform Moment Methods for Improved Interconnection Analysis. 406-412 - K. Adamiak, R. Allen, J. Poltz, C. Rebizant, A. Wexler:
System Simulation of Printed Circuit Boards Including Packages and Connectors. 413-418
Object-Oriented Approaches
- Wayne Bower, Carl Seaquist, Wayne H. Wolf:
A Framework for Industrial Layout Generators. 419-424 - Jiri Soukup:
Organized C: A Unified Method of Handling Data in CAD Algorithms and Databases. 425-430 - Moon-Jung Chung, Sangchul Kim:
An Object-Oriented VHDL Design Environment. 431-436 - S. J. Feghhi, Michael M. Marefat, Rangasami L. Kashyap:
An Object-Oriented Kernel for an Integrated Design and Process Planning System. 437-443
Scheduling Algorithms for High-Level Synthesis
- Roni Potasman, Joseph Lis, Alexandru Nicolau, Daniel Gajski:
Percolation Based Synthesis. 444-449 - Raul Compasano, Reinaldo A. Bergamaschi:
Synthesis Using Path-Based scheduling: algorithms and Exercises. 450-455 - Josef Scheichenzuber, Werner Grass, Ulrich Lauther, Sabine März:
Global Hardware Synthesis from Behavioral Dataflow Descriptions. 456-461
Layout Synthesis: Leaf Cell Generation
- Uminder Singh, C. Y. Roger Chen:
A Transistor Reordering Technique for Gate Matrix Layout. 462-467 - Knut M. Just, Edgar Auer, Werner L. Schiele, Alexander Schwaferts:
PALACE: A Kayout Generator for SCVS Logic Blocks. 468-473 - Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: A Cell Layout Generator. 474-479
Accelerating Logic Simulation
- Peter M. Maurer, Zhicheng Wang:
Techniques for Unit-Delay Compiled Simulation. 480-484 - Krishnamurthy Subramanian, Mehdi R. Zargham:
Distributed and Parallel Demand Driven Logic Simulation. 485-490 - Zhicheng Wang, Peter M. Maurer:
LECSIM: A Levelized Event Driven Compiled Logic Simulation. 491-496
Panel
- A. Richard Newton:
Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract). DAC 1990: 497-498
Data Path Synthesis
- Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu:
Data Path Allocation Based on Bipartite Weighted Matching. 499-504 - Nam Sung Woo:
A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System. 505-510 - Kayhan Küçükçakar, Alice C. Parker:
Data Path Tradeoffs Using MABAL. 511-516
Tutorial: Symbolic Simulation - Techniques and Applications
- Randal E. Bryant:
Symbolic Simulation - Techniques and Applications. 517-521
Testing Systems
- Eun Sei Park, M. Ray Mercer:
An Efficient Delay Test Generation System for Combinational Logic Circuits. 522-528 - Noriyuki Ito:
Automatic Incorporation of On-Chip Testability Circuits. 529-534 - Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel:
Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator. 535-540
Panel
- William Lattin:
Integration of Hardware and Software in Embedded Systems Design (Panel Abstract). DAC 1990: 541
Applications of Behavioral Synthesis
- Maurício Breternitz Jr., John Paul Shen:
Architecture Synthesis of High-Performance Application-Specific Processors. 542-548 - Robin C. Sarma, Mark D. Dooley, N. Craig Newman, Graham Hetherington:
High-Level Synthesis: Technology Transfer to Industry. 549-554 - Patrick Edmond, Anurag P. Gupta, Daniel P. Siewiorek, Audrey A. Brennan:
ASSURE: Automated Design for Dependability. 555-560
Performance Constrained Routing
- Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli:
Constraint Generation for Routing Analog Circuits. 561-566 - Jonathan W. Greene, Vwani P. Roychowdhury, Sinan Kaptanoglu, Abbas El Gamal:
Segmented Channel Routing. 567-572 - Michael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh:
Clock Routing for High-Performance ICs. 573-579
Testing Using Functional Models
- Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Sequential Test Generation at the Register-Transfer and Logic Levels. 580-586 - P. C. Ward, James R. Armstrong:
Behavioral Fault Simulation in VHDL. 587-593 - Ramachandra P. Kunda, Jacob A. Abraham, Bharat Deep Rathi, Prakash Narain:
Speed Up of Test Generation Using High-Level Primitives. 594-599
Panel
- Kurt Keutzer:
Impact and Evaluation of Competing Implementation Media for ASIC's (Panel Abstract). DAC 1990: 600
Decomposition and Partitioning in Logic Synthesis
- Pranav Ashar, Srinivas Devadas, A. Richard Newton:
A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines. 601-606 - Sujit Dey, Franc Brglez, Gershon Kedem:
Corolla Based Circuit Partitioning and Resynthesis. 607-612 - Robert J. Francis, Jonathan Rose, Kevin Chung:
Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. 613-619 - Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic Synthesis for Programmable Gate Arrays. 620-625
New Approaches to Routing Problems
- Werner L. Schiele, Thomas Krüger, Knut M. Just, F. H. Kirsch:
A Gridless Router for Industrial Design Rules. 626-631 - Ramin Hojati:
Layout Optimization by Pattern Modification. 632-637 - Yang Cai, D. F. Wong:
A Channel/Switchbox Definition Algorithm for Building-Block Layout. 638-641 - Masato Edahiro, Takeshi Yoshimura:
New Placement and Global Routing Algorithms for Standard Cell Layouts. 642-645 - Masao Sato, Kazuto Kubota, Tatsuo Ohtsuki:
A Hardware Implementation of Gridless Routing Based on Content Addressable Memory. 646-649 - Randall J. Brouwer, Prithviraj Banerjee:
PHIGURE: A Parallel Hierarchical Global Router. 650-653
Combinational Test Generation
- Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell:
Automatic Test Generation Using Quadratic 0-1 Programming. 654-659 - Hyung Ki Lee, Dong Sam Ha:
SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. 660-666 - John Giraldi, Michael L. Bushnell:
EST: The New Frontier in Automatic Test-Pattern Generation. 667-672 - Kenneth M. Butler, M. Ray Mercer:
The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. 673-678
Panel
- Tim Andrews:
Object Databases in Electronic Design: Implementation Experiences (Panel Abstract). DAC 1990: 679
Alternative Approaches to Behavioral Synthesis
- Gregory S. Whitcomb, A. Richard Newton:
Abstract Data Types and High-Level Synthesis. 680-685 - Ajay J. Daga, William P. Birmingham:
Failure Recovery in the MICON System. 686-691 - Wayne H. Wolf:
The FSM Network Model for Behavioral Synthesis of Control-Dominated Machines. 692-697
Channel-Oriented Multilayer Routing
- Roshan A. Gidwani, Naveed A. Sherwani:
MISER: An Integrated Three Layer Gridless Channel Router and Compactor. 698-703 - Evagelos Katsadas, Edwin Kinnen:
A Multi-Layer Router Utilizing Over-Cell Areas. 704-708 - Jason Cong, Bryan Preas, C. L. Liu:
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. 709-715
Ideas in Testing
- Tyh-Song Hwang, Chung Len Lee, Wen-Zen Shen, Ching Ping Wu:
A Parallel Pattern Mixed-Level Fault Simulator. 716-719 - T. Ramakrishnan, L. Kinney:
Extension of the Critical Path Tracing Algorithm. 720-723 - Shambhu J. Upadhyaya, John A. Thodiyil:
BIST PLAs, Pass or Fail - A Case Study. 724-727 - Weiwei Mao, Michael D. Ciletti:
A Variable Observation Time Method for Testing Delay Faults. 728-731 - Tah-Yuan Kuo, Jau-Yien Lee, Jhing-Fa Wang:
A Fault Analysis Method for Synchronous Sequential Circuits. 732-735 - Sreejit Chakravarty:
On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). 736-739
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