"An Efficient Delay Test Generation System for Combinational Logic Circuits."

Eun Sei Park, M. Ray Mercer (1990)

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DOI: 10.1145/123186.123390

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Eun Sei Park, M. Ray Mercer:
An Efficient Delay Test Generation System for Combinational Logic Circuits. DAC 1990: 522-528

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