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ORCIDKarem A. Sakallah
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- affiliation: University of Michigan, Ann Arbor, USA
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2020 – today
- 2024
[c114]Yun-Rong Luo, Aman Goel, Karem A. Sakallah:
SAT-Based Quantified Symmetric Minimization of the Reachable States of Distributed Protocols: An Update. ISoLA (3) 2024: 374-384- 2023
- [j34]Aman Goel
, Karem A. Sakallah:
Regularity and quantification: a new approach to verify distributed protocols. Innov. Syst. Softw. Eng. 19(4): 359-377 (2023) - [c113]Katalin Fazekas, Aman Goel, Karem A. Sakallah:
SAT-Based Quantified Symmetric Minimization of the Reachable States of Distributed Protocols. FMCAD 2023: 152-161 - [c112]Aman Goel, Stephan Merz, Karem A. Sakallah:
Towards an Automatic Proof of the Bakery Algorithm. FORTE 2023: 21-28 - 2021
- [c111]Aman Goel, Karem A. Sakallah:
Towards an Automatic Proof of Lamport's Paxos. FMCAD 2021: 112-122 - [c110]Aman Goel, Karem A. Sakallah:
On Symmetry and Quantification: A New Approach to Verify Distributed Protocols. NFM 2021: 131-150 - [c109]Karem A. Sakallah:
Invited Talk: AVR: Word-Level Verification by Equality Abstraction of Data State. SMT 2021: 2 - [p2]Karem A. Sakallah:
Symmetry and Satisfiability. Handbook of Satisfiability 2021: 509-570 - [i5]Aman Goel, Karem A. Sakallah:
On Symmetry and Quantification: A New Approach to Verify Distributed Protocols. CoRR abs/2103.14831 (2021) - [i4]Aman Goel, Karem A. Sakallah:
Towards an Automatic Proof of Lamport's Paxos. CoRR abs/2108.08796 (2021) - 2020
- [c108]Denis Bueno, Arlen Cox, Karem A. Sakallah:
EUFicient Reachability in Software with Arrays. FMCAD 2020: 57-66 - [c107]Aman Goel, Karem A. Sakallah:
AVR: Abstractly Verifying Reachability. TACAS (1) 2020: 413-422
2010 – 2019
- 2019
- [c106]Aman Goel, Karem A. Sakallah:
Empirical Evaluation of IC3-Based Model Checking Techniques on Verilog RTL Designs. DATE 2019: 618-621 - [c105]Haojun Ma, Aman Goel, Jean-Baptiste Jeannin, Manos Kapritsos, Baris Kasikci, Karem A. Sakallah:
Towards Automatic Inference of Inductive Invariants. HotOS 2019: 30-36 - [c104]Aman Goel, Karem A. Sakallah:
Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction. NFM 2019: 166-185 - [c103]Haojun Ma, Aman Goel, Jean-Baptiste Jeannin, Manos Kapritsos, Baris Kasikci, Karem A. Sakallah:
I4: incremental inference of inductive invariants for verification of distributed protocols. SOSP 2019: 370-384 - [c102]Denis Bueno, Karem A. Sakallah:
euforia: Complete Software Model Checking with Uninterpreted Functions. VMCAI 2019: 363-385 - 2014
- [c101]Suho Lee, Karem A. Sakallah:
Unbounded Scalable Verification Based on Approximate Property-Directed Reachability and Datapath Abstraction. CAV 2014: 849-865 - 2013
- [c100]Hadi Katebi, Karem A. Sakallah, Igor L. Markov:
Generalized Boolean symmetries through nested partition refinement. ICCAD 2013: 763-770 - [c99]Paolo Codenotti, Hadi Katebi, Karem A. Sakallah, Igor L. Markov:
Conflict Analysis and Branching Heuristics in the Search for Graph Automorphisms. ICTAI 2013: 907-914 - [c98]Denis Bueno, Kevin J. Compton, Karem A. Sakallah, Michael D. Bailey:
Detecting Traditional Packers, Decisively. RAID 2013: 184-203 - 2012
- [c97]Hadi Katebi, Karem A. Sakallah, Igor L. Markov:
Graph Symmetry Detection and Canonical Labeling: Differences and Synergies. Turing-100 2012: 181-195 - [c96]Hadi Katebi, Karem A. Sakallah, Igor L. Markov:
Conflict Anticipation in the Search for Graph Automorphisms. LPAR 2012: 243-257 - [i3]Hadi Katebi, Karem A. Sakallah, Igor L. Markov:
Conflict Anticipation in the Search for Graph Automorphisms. CoRR abs/1208.6269 (2012) - [i2]Hadi Katebi, Karem A. Sakallah, Igor L. Markov:
Graph Symmetry Detection and Canonical Labeling: Differences and Synergies. CoRR abs/1208.6271 (2012) - 2011
- [j33]Karem A. Sakallah, João Marques-Silva:
Anatomy and Empirical Evaluation of Modern SAT Solvers. Bull. EATCS 103: 96-121 (2011) - [c95]Heqing Huang, Su Zhang, Xinming Ou, Atul Prakash, Karem A. Sakallah:
Distilling critical attack graph surface iteratively through minimum-cost SAT solving. ACSAC 2011: 31-40 - [c94]Mahmoud Said, Chao Wang, Zijiang Yang, Karem A. Sakallah:
Generating Data Race Witnesses by an SMT-Based Analysis. NASA Formal Methods 2011: 313-327 - [c93]Hadi Katebi, Karem A. Sakallah, João P. Marques Silva:
Empirical Study of the Anatomy of Modern Sat Solvers. SAT 2011: 343-356 - [e2]Karem A. Sakallah, Laurent Simon:
Theory and Applications of Satisfiability Testing - SAT 2011 - 14th International Conference, SAT 2011, Ann Arbor, MI, USA, June 19-22, 2011. Proceedings. Lecture Notes in Computer Science 6695, Springer 2011, ISBN 978-3-642-21580-3 [contents] - [i1]Fadi A. Aloul, Igor L. Markov, Arathi Ramani, Karem A. Sakallah:
Breaking Instance-Independent Symmetries In Exact Graph Coloring. CoRR abs/1109.2347 (2011) - 2010
- [c92]Jina Huh, Martha E. Pollack, Hadi Katebi, Karem A. Sakallah, Ned Kirsch:
Incorporating user control in automated interactive scheduling systems. Conference on Designing Interactive Systems 2010: 306-309 - [c91]Zijiang Yang, Karem A. Sakallah:
Trace-Driven Verification of Multithreaded Programs. ICFEM 2010: 404-419 - [c90]Hadi Katebi, Karem A. Sakallah, Igor L. Markov:
Symmetry and Satisfiability: An Update. SAT 2010: 113-127
2000 – 2009
- 2009
- [j32]Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Dynamic symmetry-breaking for Boolean satisfiability. Ann. Math. Artif. Intell. 57(1): 59-73 (2009) - [j31]Mark H. Liffiton, Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva, Karem A. Sakallah:
A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas. Constraints An Int. J. 14(4): 415-442 (2009) - [c89]Zijiang Yang, Bashar Al-Rawi, Karem A. Sakallah, Xiaowan Huang, Scott A. Smolka, Radu Grosu:
Dynamic Path Reduction for Software Model Checking. IFM 2009: 322-336 - [c88]Mark H. Liffiton, Karem A. Sakallah:
Generalizing Core-Guided Max-SAT. SAT 2009: 481-494 - [p1]Karem A. Sakallah:
Symmetry and Satisfiability. Handbook of Satisfiability 2009: 289-338 - 2008
- [j30]Mark H. Liffiton, Karem A. Sakallah:
Algorithms for Computing Minimal Unsatisfiable Subsets of Constraints. J. Autom. Reason. 40(1): 1-33 (2008) - [c87]Paul T. Darga, Karem A. Sakallah, Igor L. Markov:
Faster symmetry discovery using sparsity of symmetries. DAC 2008: 149-154 - [c86]Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah:
Reveal: A Formal Verification Tool for Verilog Designs. LPAR 2008: 343-352 - [c85]Mark H. Liffiton, Karem A. Sakallah:
Searching for Autarkies to Trim Unsatisfiable Clause Sets. SAT 2008: 182-195 - 2007
- [j29]João Marques-Silva, Karem A. Sakallah, Inês Lynce:
Report on the SAT 2007 Conference on Theory and Applications of Satisfiability Testing. AI Mag. 28(4): 135-136 (2007) - [j28]Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Symmetry breaking for pseudo-Boolean formulas. ACM J. Exp. Algorithmics 12: 1.3:1-1.3:14 (2007) - [j27]Fadi A. Aloul, Arathi Ramani, Karem A. Sakallah, Igor L. Markov:
Solution and Optimization of Systems of Pseudo-Boolean Constraints. IEEE Trans. Computers 56(10): 1415-1424 (2007) - [c84]Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah:
Improved Design Debugging Using Maximum Satisfiability. FMCAD 2007: 13-19 - [e1]João Marques-Silva, Karem A. Sakallah:
Theory and Applications of Satisfiability Testing - SAT 2007, 10th International Conference, Lisbon, Portugal, May 28-31, 2007, Proceedings. Lecture Notes in Computer Science 4501, Springer 2007, ISBN 978-3-540-72787-3 [contents] - 2006
- [j26]Arathi Ramani, Igor L. Markov, Karem A. Sakallah, Fadi A. Aloul:
Breaking Instance-Independent Symmetries In Exact Graph Coloring. J. Artif. Intell. Res. 26: 289-322 (2006) - [j25]Hossein M. Sheini, Karem A. Sakallah:
Pueblo: A Hybrid Pseudo-Boolean SAT Solver. J. Satisf. Boolean Model. Comput. 2(1-4): 165-189 (2006) - [j24]Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov:
Efficient Symmetry Breaking for Boolean Satisfiability. IEEE Trans. Computers 55(5): 549-558 (2006) - [c83]Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah:
Refinement strategies for verification methods based on datapath abstraction. ASP-DAC 2006: 19-24 - [c82]Hossein M. Sheini, Karem A. Sakallah:
Ario: A Linear Integer Arithmetic Logic Solver. FMCAD 2006: 47-48 - [c81]Hossein M. Sheini, Karem A. Sakallah:
SMT(CLU): a step toward scalability in system verification. ICCAD 2006: 844-851 - [c80]Hossein M. Sheini, Karem A. Sakallah:
From Propositional Satisfiability to Satisfiability Modulo Theories. SAT 2006: 1-9 - [c79]Hossein M. Sheini, Karem A. Sakallah:
A Progressive Simplifier for Satisfiability Modulo Theories. SAT 2006: 184-197 - 2005
- [j23]Maher N. Mneimneh, Karem A. Sakallah:
Principles of Sequential-Equivalence Verification. IEEE Des. Test Comput. 22(3): 248-257 (2005) - [c78]Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Dynamic symmetry-breaking for improved Boolean optimization. ASP-DAC 2005: 445-450 - [c77]Hossein M. Sheini, Bart Peintner, Karem A. Sakallah, Martha E. Pollack:
On Solving Soft Temporal Constraints Using SAT Techniques. CP 2005: 607-621 - [c76]Hossein M. Sheini, Karem A. Sakallah:
A SAT-Based Decision Procedure for Mixed Logical/Integer Linear Problems. CPAIOR 2005: 320-335 - [c75]Hossein M. Sheini, Karem A. Sakallah:
Pueblo: A Modern Pseudo-Boolean SAT Solver. DATE 2005: 684-685 - [c74]Mark H. Liffiton, Michael D. Moffitt, Martha E. Pollack, Karem A. Sakallah:
Identifying Conflicts in Overconstrained Temporal Problems. IJCAI 2005: 205-211 - [c73]Mark H. Liffiton, Karem A. Sakallah:
On Finding All Minimally Unsatisfiable Subformulas. SAT 2005: 173-186 - [c72]Hossein M. Sheini, Karem A. Sakallah:
A Scalable Method for Solving Satisfiability of Integer Linear Arithmetic Logic. SAT 2005: 241-256 - [c71]Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva, Karem A. Sakallah:
A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas. SAT 2005: 467-474 - 2004
- [j22]Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
MINCE: A Static Global Variable-Ordering Heuristic for SAT Search and BDD Manipulation. J. Univers. Comput. Sci. 10(12): 1562-1596 (2004) - [j21]Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar:
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. IEEE Trans. Computers 53(6): 688-696 (2004) - [c70]Maher N. Mneimneh, Karem A. Sakallah, John Moondanos:
Preserving synchronizing sequences of sequential circuits after retiming. ASP-DAC 2004: 579-584 - [c69]Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
ShatterPB: symmetry-breaking for pseudo-Boolean formulas. ASP-DAC 2004: 883-886 - [c68]Zaher S. Andraus, Karem A. Sakallah:
Automatic abstraction and verification of verilog models. DAC 2004: 218-223 - [c67]Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov:
AMUSE: a minimally-unsatisfiable subformula extractor. DAC 2004: 518-523 - [c66]Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, Igor L. Markov:
Exploiting structure in symmetry detection for CNF. DAC 2004: 530-534 - [c65]Arathi Ramani, Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Breaking Instance-Independent Symmetries in Exact Graph Coloring. DATE 2004: 324-331 - 2003
- [j20]Hui Xu, Rob A. Rutenbar, Karem A. Sakallah:
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 814-820 (2003) - [j19]Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah:
Satometer: how much have we searched? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 995-1004 (2003) - [j18]Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Solving difficult instances of Boolean satisfiability in the presence of symmetry. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1117-1137 (2003) - [j17]Michael A. Riepe, Karem A. Sakallah:
Transistor placement for noncomplementary digital VLSI cell synthesis. ACM Trans. Design Autom. Electr. Syst. 8(1): 81-107 (2003) - [c64]Maher N. Mneimneh, Karem A. Sakallah:
SAT-based sequential depth computation. ASP-DAC 2003: 87-92 - [c63]Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Shatter: efficient symmetry-breaking for boolean satisfiability. DAC 2003: 836-839 - [c62]Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
FORCE: a fast and easy-to-implement variable-ordering heuristic. ACM Great Lakes Symposium on VLSI 2003: 116-119 - [c61]Fadi A. Aloul, Karem A. Sakallah, Igor L. Markov:
Efficient Symmetry Breaking for Boolean Satisfiability. IJCAI 2003: 271-276 - [c60]Maher N. Mneimneh, Karem A. Sakallah:
Computing Vertex Eccentricity in Exponentially Large Graphs: QBF Formulation and Solution. SAT 2003: 411-425 - 2002
- [j16]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
A new FPGA detailed routing approach via search-based Booleansatisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 674-684 (2002) - [j15]Luís Guerra e Silva, João Marques-Silva, Luís Miguel Silveira, Karem A. Sakallah:
Satisfiability models and algorithms for circuit delay computation. ACM Trans. Design Autom. Electr. Syst. 7(1): 137-158 (2002) - [c59]Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Solving difficult SAT instances in the presence of symmetry. DAC 2002: 731-736 - [c58]Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah:
Satometer: how much have we searched? DAC 2002: 737-742 - [c57]Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah:
Search-Based SAT Using Zero-Suppressed BDDs. DATE 2002: 1082 - [c56]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. FPL 2002: 360-369 - [c55]Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Generic ILP versus specialized 0-1 ILP: an update. ICCAD 2002: 450-457 - [c54]Victor N. Kravets, Karem A. Sakallah:
Resynthesis of multi-level circuits under tight constraints using symbolic optimization. ICCAD 2002: 687-693 - [c53]Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering. ICCD 2002: 64-69 - [c52]Hui Xu, Rob A. Rutenbar, Karem A. Sakallah:
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. ISPD 2002: 182-187 - [c51]Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah:
ZBDD-Based Backtrack Search SAT Solver. IWLS 2002: 131-136 - [c50]Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Efficient Gate and Input Ordering for Circuit-to-BDD Conversion. IWLS 2002: 137-142 - [c49]Leyla Nazhandali, Karem A. Sakallah:
Majority-Based Decomposition of Carry Logic in Binary Adders. IWLS 2002: 179-184 - [c48]Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David T. Blaauw:
Robust SAT-Based Search Algorithm for Leakage Power Reduction. PATMOS 2002: 167-177 - 2001
- [j14]Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes:
Fast and accurate timing characterization using functionalinformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 315-331 (2001) - [c47]Maher N. Mneimneh, Fadi A. Aloul, Christopher T. Weaver, Saugata Chatterjee, Karem A. Sakallah, Todd M. Austin:
Scalable Hybrid Verification of Complex Microprocessors. DAC 2001: 41-46 - [c46]Jesse Whittemore, Joonyoung Kim, Karem A. Sakallah:
SATIRE: A New Incremental Satisfiability Engine. DAC 2001: 542-545 - [c45]Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes:
An Advanced Timing Characterization Method Using Mode Dependency. DAC 2001: 657-660 - [c44]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
A boolean satisfiability-based incremental rerouting approach with application to FPGAs. DATE 2001: 560-565 - [c43]Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Faster SAT and Smaller BDDs via Common Function Structure. ICCAD 2001: 443-448 - [c42]Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar:
A comparative study of two Boolean formulations of FPGA detailed routing constraints. ISPD 2001: 222-227 - 2000
- [c41]João Marques-Silva, Karem A. Sakallah:
Invited Tutorial: Boolean Satisfiability Algorithms and Applications in Electronic Design Automation. CAV 2000: 3 - [c40]João P. Marques Silva, Karem A. Sakallah:
Boolean satisfiability in electronic design automation. DAC 2000: 675-680 - [c39]Victor N. Kravets, Karem A. Sakallah:
Constructive Library-Aware Synthesis Using Symmetries. DATE 2000: 208-213 - [c38]Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah, João P. Marques Silva:
On Applying Incremental Satisfiability to Delay Fault Testing. DATE 2000: 380-384 - [c37]Karem A. Sakallah, Fadi A. Aloul, João P. Marques Silva:
An Experimental Study of Satisfiability Search Heuristics. DATE 2000: 745 - [c36]Victor N. Kravets, Karem A. Sakallah:
Generalized Symmetries in Boolean Functions. ICCAD 2000: 526-532 - [c35]Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah:
On Solving Stack-Based Incremental Satisfiability Problems. ICCD 2000: 379-382
1990 – 1999
- 1999
- [j13]João P. Marques Silva, Karem A. Sakallah:
GRASP: A Search Algorithm for Propositional Satisfiability. IEEE Trans. Computers 48(5): 506-521 (1999) - [j12]David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah:
Timing verification of sequential dynamic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 645-658 (1999) - [c34]Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah:
Functional Timing Analysis for IP Characterization. DAC 1999: 731-736 - [c33]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. FPGA 1999: 167-175 - [c32]Joonyoung Kim, João Marques-Silva, Karem A. Sakallah:
Satisfiability-Based Functional Delay Fault Testing. VLSI 1999: 362-372 - [c31]Michael A. Riepe, Karem A. Sakallah:
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis. ISPD 1999: 74-81 - [c30]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Satisfiability-Based Detailed FPGA Routing. VLSI Design 1999: 574-577 - 1998
- [j11]Michael A. Riepe, Karem A. Sakallah:
The edge-based design rule model revisited. ACM Trans. Design Autom. Electr. Syst. 3(3): 463-486 (1998) - [j10]Richard B. Brown, Bruce Bernhardt, M. LaMacchia, J. Abrokwah, Phiroze N. Parakh, Todd D. Basso, Spencer M. Gold, S. Stetson, Claude R. Gauthier, D. Foster, B. Crawforth, T. McQuire, Karem A. Sakallah, Ronald J. Lomax, Trevor N. Mudge:
Overview of complementary GaAs technology for high-speed VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 47-51 (1998) - [c29]Phiroze N. Parakh, Richard B. Brown, Karem A. Sakallah:
Congestion Driven Quadratic Placement. DAC 1998: 275-278 - [c28]Victor N. Kravets, Karem A. Sakallah:
M32: A Constructive multilevel Logic Synthesis System. DAC 1998: 336-341 - [c27]V. Chandramouli, Jesse Whittemore, Karem A. Sakallah:
AFTA: A Formal Delay Model for Functional Timing Analysis. DATE 1998: 350-355 - [c26]Luís Guerra e Silva, João P. Marques Silva, Luís Miguel Silveira, Karem A. Sakallah:
Timing analysis using propositional satisfiability. ICECS 1998: 95-98 - 1997
- [c25]V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi:
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity. ARVLSI 1997: 32-46 - [c24]João P. Marques Silva, Karem A. Sakallah:
Robust Search Algorithms for Test Pattern Generation. FTCS 1997: 152-161 - 1996
- [j9]Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown:
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 113-129 (1996) - [c23]V. Chandramouli, Karem A. Sakallah:
Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time. DAC 1996: 617-622 - [c22]Hakan Yalcin, John P. Hayes, Karem A. Sakallah:
An approximate timing analysis method for datapath circuits. ICCAD 1996: 114-118 - [c21]David Van Campenhout, Trevor N. Mudge, Karem A. Sakallah:
Timing verification of sequential domino circuits. ICCAD 1996: 127-132 - [c20]João P. Marques Silva, Karem A. Sakallah:
GRASP - a new search algorithm for satisfiability. ICCAD 1996: 220-227 - [c19]João P. Marques Silva, Karem A. Sakallah:
Conflict Analysis in Search Algorithms for Satisfiability. ICTAI 1996: 467-469 - 1995
- [j8]Ayman I. Kayssi, Karem A. Sakallah:
Timing models for gallium arsenide direct-coupled FET logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 384-393 (1995) - [j7]Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah:
Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1526-1545 (1995) - [j6]Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge:
Critical paths in circuits with level-sensitive latches. IEEE Trans. Very Large Scale Integr. Syst. 3(2): 273-291 (1995) - [c18]Ajay Chandna, C. David Kibler, Richard B. Brown, Mark Roberts, Karem A. Sakallah:
The Aurora RAM Compiler. DAC 1995: 261-266 - 1994
- [c17]João P. Marques Silva, Karem A. Sakallah:
Dynamic Search-Space Pruning Techniques in Path Sensitization. DAC 1994: 705-711 - [c16]Timothy M. Burks, Karem A. Sakallah:
Optimization of critical paths in circuits with level-sensitive latches. ICCAD 1994: 468-473 - [c15]João P. Marques Silva, Karem A. Sakallah:
Efficient and Robust Test Generation-Based Timing Analysis. ISCAS 1994: 303-306 - [c14]Ayman I. Kayssi, Karem A. Sakallah:
Macromodel Simplification Using Dimensional Analysis. ISCAS 1994: 335-338 - 1993
- [j5]Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson:
Synchronization of pipelines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1132-1146 (1993) - [c13]João P. Marques Silva, Karem A. Sakallah:
Concurrent path sensitization in timing analysis. EURO-DAC 1993: 196-199 - [c12]Timothy M. Burks, Karem A. Sakallah:
Min-max linear programming and the timing analysis of digital circuits. ICCAD 1993: 152-155 - [c11]João P. Marques Silva, Karem A. Sakallah:
An Analysis of Path Sensitization Criteria. ICCD 1993: 68-72 - [c10]Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown:
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation. ICCD 1993: 361-364 - 1992
- [j4]Karem A. Sakallah, Trevor N. Mudge, Oyekunle A. Olukotun:
Analysis and design of latch-controlled synchronous digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3): 322-333 (1992) - [c9]Ayman I. Kayssi, Karem A. Sakallah:
Delay macromodels for the timing analysis of GaAs DCFL. EURO-DAC 1992: 142-145 - [c8]Timothy M. Burks, Karem A. Sakallah, Trevor N. Mudge:
Identification of critical paths in circuits with level-sensitive latches. ICCAD 1992: 137-141 - [c7]Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah:
Using constraint geometry to determine maximum rate pipeline clocking. ICCAD 1992: 142-148 - [c6]Emily J. Shriver, Karem A. Sakallah:
Ravel: assigned-delay compiled-code logic simulation. ICCAD 1992: 364-368 - 1991
- [j3]Trevor N. Mudge, Richard B. Brown, William P. Bimingham, Jeffrey A. Dykstra, Ayman I. Kayssi, Ronald J. Lomax, Kunle Olukotun, Karem A. Sakallah, Raymond A. Milano:
The Design of a Microsupercomputer. Computer 24(1): 57-64 (1991) - [c5]João P. Marques Silva, Karem A. Sakallah, Luís M. Vidigal:
FPD - An Environment for Exact Timing Analysis. ICCAD 1991: 212-215 - [c4]Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson:
Optimal Clocking of Circular Pipelines. ICCD 1991: 642-650 - 1990
- [j2]Karem A. Sakallah, Yao-Tsung Yen, Steve S. Greenberg:
A first-order charge conserving MOS capacitance model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1): 99-108 (1990) - [c3]Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun:
Analysis and Design of Latch-Controlled Synchronous Digital Circuits. DAC 1990: 111-117 - [c2]Karem A. Sakallah, Trevor N. Mudge, Kunle Olukotun:
check Tc and min Tc: Timing Verification and Optimal Clocking of Synchronous Digtal Circuits. ICCAD 1990: 552-555 - [c1]Somanathan C. Menon, Karem A. Sakallah:
Clock Qualification Algorithm for Timing Analysis of Custom CMOS VLSI Circuits with Overlapped Clocking Disciplines and On-section Clock Derivation. ICSI 1990: 550-558
1980 – 1989
- 1985
- [j1]Karem A. Sakallah, Stephen W. Director:
SAMSON2: An Event Driven VLSI Circuit Simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(4): 668-684 (1985)
Coauthor Index
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