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ORCIDJohn P. Hayes
John Patrick Hayes
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- affiliation: University of Michigan, Ann Arbor, USA
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2020 – today
- 2024
[c145]Roshwin Sengupta, Ilia Polian, John P. Hayes:
Performance and Error Tolerance of Stochastic Computing-Based Digital Filter Design. DDECS 2024: 7-12- 2023
- [c144]Timothy J. Baker, John P. Hayes:
Design of Large-Scale Stochastic Computing Adders and their Anomalous Behavior. DATE 2023: 1-6 - [c143]Florian Neugebauer, Vivek Vekariya, Ilia Polian, John P. Hayes:
Stochastic Computing as a Defence Against Adversarial Attacks. DSN-W 2023: 191-194 - [c142]Owen Hoffend, John P. Hayes:
Mitigating the Correlation Problem in Multi-Layer Stochastic Circuits. ICRC 2023: 1-10 - 2022
- [j113]Timothy J. Baker
, John P. Hayes:
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design. ACM Trans. Design Autom. Electr. Syst. 27(3): 27:1-27:26 (2022) - [c141]Roshwin Sengupta, Ilia Polian, John P. Hayes:
Stochastic Computing Architectures for Lightweight LSTM Neural Networks. DDECS 2022: 124-129 - [c140]Owen Hoffend, John P. Hayes:
Analyzing Multilevel Stochastic Circuits using Correlation Matrices. DDECS 2022: 130-135 - [c139]Roshwin Sengupta, Ilia Polian, John P. Hayes:
Wavelet Transform Assisted Neural Networks for Human Activity Recognition. ISCAS 2022: 1254-1258 - [c138]Timothy J. Baker, Owen Hoffend, John P. Hayes:
Multiplexer-Majority Chains: Managing Correlation and Cost in Stochastic Number Generation. NANOARCH 2022: 21:1-21:6 - 2021
- [j112]Ilia Polian, John P. Hayes, Vincent T. Lee, Weikang Qian:
Guest Editors' Introduction: Stochastic Computing for Neuromorphic Applications. IEEE Des. Test 38(6): 5-15 (2021) - [c137]Timothy J. Baker, Yiqiu Sun, John P. Hayes:
Benefits of Stochastic Computing in Hearing Aid Filterbank Design. BioCAS 2021: 1-5 - [i3]Timothy J. Baker, John P. Hayes:
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design. CoRR abs/2108.12326 (2021) - 2020
- [c136]Timothy J. Baker, John P. Hayes:
The Hypergeometric Distribution as a More Accurate Model for Stochastic Computing. DATE 2020: 592-597 - [c135]Chen Wang, Weihua Xiao, John P. Hayes, Weikang Qian:
Exploring Target Function Approximation for Stochastic Circuit Minimization. ICCAD 2020: 122:1-122:9 - [c134]Timothy J. Baker, John P. Hayes:
Bayesian Accuracy Analysis of Stochastic Circuits. ICCAD 2020: 124:1-124:9 - [c133]Ponnanna Kelettira Muthappa, Florian Neugebauer, Ilia Polian, John P. Hayes:
Hardware-based Fast Real-time Image Classification with Stochastic Computing. ICCD 2020: 340-347 - [c132]Junseok Oh, Florian Neugebauer, Ilia Polian, John P. Hayes:
Retraining and Regularization to Optimize Neural Networks for Stochastic Computing. ISVLSI 2020: 246-251
2010 – 2019
- 2019
- [j111]Pai-Shun Ting, John P. Hayes:
Removing constant-induced errors in stochastic circuits. IET Comput. Digit. Tech. 13(3): 187-197 (2019) - [j110]Te-Hsuan Chen, John P. Hayes:
Equivalence Among Stochastic Logic Circuits and its Application to Synthesis. IEEE Trans. Emerg. Top. Comput. 7(1): 67-79 (2019) - [c131]Florian Neugebauer, Ilia Polian, John P. Hayes:
On the maximum function in stochastic computing. CF 2019: 59-66 - [c130]Pai-Shun Ting, John P. Hayes:
Exploiting Randomness in Stochastic Computing. ICCAD 2019: 1-6 - [c129]Florian Neugebauer, Ilia Polian, John P. Hayes:
On the Limits of Stochastic Computing. ICRC 2019: 98-105 - [c128]Timothy J. Baker, John P. Hayes:
Impact of Autocorrelation on Stochastic Circuit Accuracy. ISVLSI 2019: 271-277 - 2018
- [j109]Dinesh A. Mirchandani, Yunus Kathawala, Julius H. Johnson Jr., John P. Hayes, Sudhir Chawla:
A comparison of perspectives of Kuwaiti and Indonesian residents towards e-government. Electron. Gov. an Int. J. 14(2): 134-159 (2018) - [j108]Florian Neugebauer, Ilia Polian, John P. Hayes:
Framework for Quantifying and Managing Accuracy in Stochastic Circuit Design. ACM J. Emerg. Technol. Comput. Syst. 14(2): 31:1-31:21 (2018) - [j107]Florian Neugebauer, Ilia Polian, John P. Hayes:
S-box-based random number generation for stochastic computing. Microprocess. Microsystems 61: 316-326 (2018) - [j106]Armin Alaghi, Weikang Qian, John P. Hayes:
The Promise and Challenge of Stochastic Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1515-1531 (2018) - [c127]Pai-Shun Ting, John P. Hayes:
Maxflow: Minimizing Latency in Hybrid Stochastic-Binary Systems. ACM Great Lakes Symposium on VLSI 2018: 21-26 - 2017
- [j105]Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Trading Accuracy for Energy in Stochastic Circuit Design. ACM J. Emerg. Technol. Comput. Syst. 13(3): 47:1-47:30 (2017) - [c126]Florian Neugebauer, Ilia Polian, John P. Hayes:
Framework for quantifying and managing accuracy in stochastic circuit design. DATE 2017: 1-6 - [c125]Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze:
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. DATE 2017: 13-18 - [c124]Pai-Shun Ting, John P. Hayes:
Eliminating a hidden error source in stochastic circuits. DFT 2017: 1-6 - [c123]Florian Neugebauer, Ilia Polian, John P. Hayes:
Building a Better Random Number Generator for Stochastic Computing. DSD 2017: 1-8 - [c122]Te-Hsuan Chen, Pai-Shun Ting, John P. Hayes:
Achieving progressive precision in stochastic computing. GlobalSIP 2017: 1320-1324 - [c121]Pai-Shun Ting, John P. Hayes:
On the Role of Sequential Circuits in Stochastic Computing. ACM Great Lakes Symposium on VLSI 2017: 475-478 - [c120]Meng Yang, John P. Hayes, Deliang Fan, Weikang Qian:
Design of accurate stochastic number generators with noisy emerging devices for stochastic computing. ICCAD 2017: 638-644 - [i2]Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze:
Energy-Efficient Hybrid Stochastic-Binary Neural Networks for Near-Sensor Computing. CoRR abs/1706.02344 (2017) - 2016
- [c119]Pai-Shun Ting, John P. Hayes:
Isolation-based decorrelation of stochastic circuits. ICCD 2016: 88-95 - [c118]Te-Hsuan Chen, John P. Hayes:
Design of Division Circuits for Stochastic Computing. ISVLSI 2016: 116-121 - 2015
- [j104]Armin Alaghi, John P. Hayes:
STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1770-1783 (2015) - [c117]John P. Hayes:
Introduction to stochastic computing and its challenges. DAC 2015: 59:1-59:3 - [c116]Te-Hsuan Chen, John P. Hayes:
Equivalence among stochastic logic circuits and its application. DAC 2015: 131:1-131:6 - [c115]I-Che Chen, John P. Hayes:
Low-Area and High-Speed Approximate Matrix-Vector Multiplier. DDECS 2015: 23-28 - [c114]Armin Alaghi, John P. Hayes:
On the Functions Realized by Stochastic Computing Circuits. ACM Great Lakes Symposium on VLSI 2015: 331-336 - [c113]Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. ICCAD 2015: 178-185 - [c112]Armin Alaghi, John P. Hayes:
Dimension reduction in statistical simulation of digital circuits. SpringSim (TMS-DEVS) 2015: 1-8 - 2014
- [j103]Te-Hsuan Chen, Armin Alaghi, John P. Hayes:
Behavior of stochastic circuits under severe error conditions. it Inf. Technol. 56(4): 182-191 (2014) - [c111]Armin Alaghi, John P. Hayes:
Fast and accurate computation using stochastic circuits. DATE 2014: 1-4 - [c110]Pai-Shun Ting, John Patrick Hayes:
Stochastic Logic Realization of Matrix Operations. DSD 2014: 356-364 - [c109]Te-Hsuan Chen, John P. Hayes:
Analyzing and controlling accuracy in stochastic circuits. ICCD 2014: 367-373 - 2013
- [b3]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Design, Analysis and Test of Logic Circuits Under Uncertainty. Lecture Notes in Electrical Engineering 115, Springer 2013, ISBN 978-90-481-9643-2, pp. 1-120 - [j102]Armin Alaghi, John P. Hayes:
Survey of Stochastic Computing. ACM Trans. Embed. Comput. Syst. 12(2s): 92:1-92:19 (2013) - [c108]Armin Alaghi, Cheng Li, John P. Hayes:
Stochastic circuits for real-time image-processing applications. DAC 2013: 136:1-136:6 - [c107]Te-Hsuan Chen, John P. Hayes:
Design of stochastic Viterbi decoders for convolutional codes. DDECS 2013: 66-71 - [c106]Alexandru Paler, Josef Kinseher, Ilia Polian, John P. Hayes:
Approximate simulation of circuits with probabilistic behavior. DFTS 2013: 95-100 - [c105]Armin Alaghi, John P. Hayes:
Exploiting correlation in stochastic circuit design. ICCD 2013: 39-46 - 2012
- [j101]Joonhwan Yi, John P. Hayes:
Robust Coupling Delay Test Sets. J. Electron. Test. 28(3): 375-388 (2012) - [j100]Kenneth M. Zick, John P. Hayes:
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems. ACM Trans. Reconfigurable Technol. Syst. 5(1): 1:1-1:26 (2012) - [c104]Alexandru Paler, Ilia Polian, John P. Hayes:
Detection and diagnosis of faulty quantum circuits. ASP-DAC 2012: 181-186 - [c103]Chien-Chih Yu, Armin Alaghi, John P. Hayes:
Scalable sampling methodology for logic simulation: Reduced-Ordered Monte Carlo. ICCAD 2012: 195-201 - [c102]Armin Alaghi, John P. Hayes:
A spectral transform approach to stochastic circuits. ICCD 2012: 315-321 - 2011
- [j99]Ilia Polian, John P. Hayes:
Selective Hardening: Toward Cost-Effective Error Tolerance. IEEE Des. Test Comput. 28(3): 54-63 (2011) - [j98]Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker:
Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Secur. Comput. 8(4): 537-547 (2011) - [c101]Dae Young Lee, David D. Wentzloff, John P. Hayes:
A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits. A-SSCC 2011: 153-156 - [c100]Chien-Chih Yu, John P. Hayes:
Trigonometric method to handle realistic error probabilities in logic circuits. DATE 2011: 64-69 - [c99]Dae Young Lee, David D. Wentzloff, John P. Hayes:
Wireless wafer-level testing of integrated circuits via capacitively-coupled channels. DDECS 2011: 99-104 - [c98]Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes:
Tomographic Testing and Validation of Probabilistic Circuits. ETS 2011: 63-68 - 2010
- [c97]Ilia Polian, John P. Hayes:
Advanced modeling of faults in Reversible circuits. EWDTS 2010: 376-381 - [c96]Kenneth M. Zick, John P. Hayes:
On-line sensing for healthier FPGA systems. FPGA 2010: 239-248 - [c95]Kenneth M. Zick, John P. Hayes:
Self-Test and Adaptation for Random Variations in Reliability. FPL 2010: 193-198 - [c94]Kenneth M. Zick, John P. Hayes:
Toward Physically-Adaptive Computing. SASO 2010: 124-133 - [c93]Chien-Chih Yu, John P. Hayes:
Scalable and accurate estimation of probabilistic behavior in sequential circuits. VTS 2010: 165-170
2000 – 2009
- 2009
- [b2]George F. Viamontes, Igor L. Markov, John P. Hayes:
Quantum Circuit Simulation. Springer 2009, ISBN 978-90-481-3064-1, pp. I-X, 1-190 - [j97]Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes:
Signature-Based SER Analysis and Design of Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 74-86 (2009) - [c92]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Improving testability and soft-error resilience through retiming. DAC 2009: 508-513 - [c91]Erik Jan Marinissen, Dae Young Lee, John P. Hayes, Chris Sellathamby, Brian Moore, Steven Slupsky, Laurence Pujol:
Contactless testing: Possibility or pipe-dream? DATE 2009: 676-681 - [c90]Kenneth M. Zick, John P. Hayes:
On-line characterization and reconfiguration for single event upset variations. IOLTS 2009: 243-248 - 2008
- [j96]Ketan N. Patel, Igor L. Markov, John P. Hayes:
Optimal synthesis of linear reversible circuits. Quantum Inf. Comput. 8(3): 282-294 (2008) - [j95]Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes:
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits. ACM Trans. Design Autom. Electr. Syst. 13(1): 8:1-8:35 (2008) - [c89]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
On the role of timing masking in reliable logic circuit design. DAC 2008: 924-929 - [c88]Kenneth M. Zick, John P. Hayes:
High-level vulnerability over space and time to insidious soft errors. HLDVT 2008: 161-168 - [c87]Sungsoon Cho, John P. Hayes:
Optimizing router locations for minimum-energy wireless networks. LCN 2008: 544-546 - 2007
- [j94]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Tracking Uncertainty with Probabilistic Logic Circuit Testing. IEEE Des. Test Comput. 24(4): 312-321 (2007) - [j93]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS. IEEE J. Solid State Circuits 42(9): 1976-1985 (2007) - [c86]Ramashis Das, John P. Hayes:
Monitoring Transient Errors in Sequential Circuits. ATS 2007: 319-322 - [c85]George F. Viamontes, Igor L. Markov, John P. Hayes:
Checking equivalence of quantum circuits and states. ICCAD 2007: 69-74 - [c84]Smita Krishnaswamy, Stephen Plaza, Igor L. Markov, John P. Hayes:
Enhancing design robustness with reliability-aware resynthesis and logic simulation. ICCAD 2007: 149-154 - [c83]Sungsoon Cho, John P. Hayes:
Power-Aware Link Maintenance (PALM) for Mobile Ad Hoc Networks. LCN 2007: 403-410 - [c82]John P. Hayes, Ilia Polian, Bernd Becker:
An Analysis Framework for Transient-Error Tolerance. VTS 2007: 249-255 - [i1]George F. Viamontes, Igor L. Markov, John P. Hayes:
Checking Equivalence of Quantum Circuits and States. CoRR abs/0705.0017 (2007) - 2006
- [j92]Aditya K. Prasad, Vivek V. Shende, Igor L. Markov, John P. Hayes, Ketan N. Patel:
Data structures and algorithms for simplifying reversible circuits. ACM J. Emerg. Technol. Comput. Syst. 2(4): 277-293 (2006) - [j91]Feng Gao, John P. Hayes:
Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction. J. Low Power Electron. 2(2): 230-239 (2006) - [j90]Joonhwan Yi, John P. Hayes:
High-level delay test generation for modular circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 576-590 (2006) - [j89]Feng Gao, John P. Hayes:
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2564-2571 (2006) - [c81]Ramashis Das, Igor L. Markov, John P. Hayes:
On-Chip Test Generation Using Linear Subspaces. ETS 2006: 111-116 - [c80]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A Fully Integrated Auto-Calibrated SuperRegenerative Receiver. ISSCC 2006: 1490-1499 - 2005
- [j88]George F. Viamontes, Igor L. Markov, John P. Hayes:
Is quantum search practical? Comput. Sci. Eng. 7(3): 62-70 (2005) - [j87]Joonhwan Yi, John P. Hayes:
The Coupling Model for Function and Delay Faults. J. Electron. Test. 21(6): 631-649 (2005) - [j86]George F. Viamontes, Igor L. Markov, John P. Hayes:
Graph-based simulation of quantum computation in the density matrix representation. Quantum Inf. Comput. 5(2): 113-130 (2005) - [j85]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Dependable communication synthesis for distributed embedded systems. Reliab. Eng. Syst. Saf. 89(1): 81-92 (2005) - [j84]Amit Chowdhary, John P. Hayes:
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 999-1013 (2005) - [j83]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis. IEEE Trans. Parallel Distributed Syst. 16(3): 258-270 (2005) - [c79]John P. Hayes:
Faults and Tests in Quantum Circuits. Asian Test Symposium 2005 - [c78]Ilia Polian, Thomas Fiehn, Bernd Becker, John P. Hayes:
A Family of Logical Fault Models for Reversible Circuits. Asian Test Symposium 2005: 422-427 - [c77]Nagarajan Kandasamy, Sherif Abdelwahed, Gregory C. Sharp, John P. Hayes:
An Online Control Framework for Designing Self-Optimizing Computing Systems: Application to Power Management. Self-star Properties in Complex Information Systems 2005: 174-188 - [c76]Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS. CICC 2005: 361-364 - [c75]Feng Gao, John P. Hayes:
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. DAC 2005: 31-36 - [c74]Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes:
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. DATE 2005: 282-287 - [c73]Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Logic circuit testing for transient faults. ETS 2005: 102-107 - [c72]Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker:
Transient fault characterization in dynamic noisy environments. ITC 2005: 10 - [c71]Sungsoon Cho, John P. Hayes:
Impact of mobility on connection in ad hoc networks. WCNC 2005: 1650-1656 - 2004
- [j82]Ketan N. Patel, John P. Hayes, Igor L. Markov:
Fault testing for reversible circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1220-1230 (2004) - [c70]John P. Hayes, Ilia Polian, Bernd Becker:
Testing for Missing-Gate Faults in Reversible Circuits. Asian Test Symposium 2004: 100-105 - [c69]George F. Viamontes, Igor L. Markov, John P. Hayes:
High-Performance QuIDD-Based Simulation of Quantum Circuits. DATE 2004: 1354-1355 - [c68]Rajesh Venkatasubramanian, John P. Hayes:
Discovering 1-FT Routes in Mobile Ad Hoc Networks. DSN 2004: 627-636 - [c67]Nagarajan Kandasamy, Sherif Abdelwahed, John P. Hayes:
Self-Optimization in Computer Systems via On-Line Control: Application to Power Management. ICAC 2004: 54-61 - [c66]Feng Gao, John P. Hayes:
Exact and heuristic approaches to input vector control for leakage power reduction. ICCAD 2004: 527-532 - [c65]Feng Gao, John P. Hayes:
Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction. ICCD 2004: 258-264 - 2003
- [j81]Feng Gao, John P. Hayes:
On-Line Monitor Design of Finite-State Machines. J. Electron. Test. 19(5): 537-548 (2003) - [j80]George F. Viamontes, Igor L. Markov, John P. Hayes:
Improving Gate-Level Simulation of Quantum Circuits. Quantum Inf. Process. 2(5): 347-380 (2003) - [j79]Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes:
Synthesis of reversible logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 710-722 (2003) - [j78]Ronald D. Blanton, John P. Hayes:
On the properties of the input pattern fault model. ACM Trans. Design Autom. Electr. Syst. 8(1): 108-124 (2003) - [c64]George F. Viamontes, Manoj Rajagopalan, Igor L. Markov, John P. Hayes:
Gate-level simulation of quantum circuits. ASP-DAC 2003: 295-301 - [c63]John P. Hayes:
Tutorial: basic concepts in quantum circuits. DAC 2003: 893 - [c62]Rajesh Venkatasubramanian, John P. Hayes, Brian T. Murray:
Low-Cost On-Line Fault Detection Using Control Flow Assertions. IOLTS 2003: 137-143 - [c61]Feng Gao, John P. Hayes:
ILP-based optimization of sequential circuits for low power. ISLPED 2003: 140-145 - [c60]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Dependable Communication Synthesis for Distributed Embedded Systems. SAFECOMP 2003: 275-288 - [c59]Ketan N. Patel, John P. Hayes, Igor L. Markov:
Fault Testing for Reversible Circuits. VTS 2003: 410-416 - 2002
- [j77]Dimitris Nikolos, John P. Hayes, Michael Nicolaidis, Cecilia Metra:
Guest Editorial. J. Electron. Test. 18(3): 259-260 (2002) - [j76]Amit Chowdhary, John P. Hayes:
General technology mapping for field-programmable gate arrays based on lookup tables. ACM Trans. Design Autom. Electr. Syst. 7(1): 1-32 (2002) - [c58]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Time-Constrained Failure Diagnosis in Distributed Embedded Systems. DSN 2002: 449-458 - [c57]Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes:
Reversible logic circuit synthesis. ICCAD 2002: 353-360 - [c56]Feng Gao, John P. Hayes:
On-Line Monitor Design of Finite-State Machines. IOLTW 2002: 74-78 - [c55]John P. Hayes:
Fault-Tolerant Quantum Computers. IPDPS 2002 - [c54]Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes:
Reversible Logic Circuit Synthesis. IWLS 2002: 125-130 - 2001
- [j75]HyungWon Kim, John P. Hayes:
Realization-independent ATPG for designs with unimplemented blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 290-306 (2001) - [j74]Hakan Yalcin, Mohammad Mortazavi, Robert Palermo, Cyrus Bamji, Karem A. Sakallah, John P. Hayes:
Fast and accurate timing characterization using functionalinformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 315-331 (2001) - [j73]HyungWon Kim, John P. Hayes:
Delay fault testing of IP-based designs via symbolic path modeling. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 661-678 (2001) - [c53]Hakan Yalcin, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Karem A. Sakallah, John P. Hayes:
An Advanced Timing Characterization Method Using Mode Dependency. DAC 2001: 657-660 - [c52]Joonhwan Yi, John P. Hayes:
A fault model for function and delay testing. ETW 2001: 27-34 - 2000
- [j72]David Van Campenhout, Trevor N. Mudge, John P. Hayes:
Collection and Analysis of Microprocessor Design Errors. IEEE Des. Test Comput. 17(4): 51-60 (2000) - [j71]Hussain Al-Asaad, John P. Hayes:
Logic Design Validation via Simulation and Automatic Test Pattern Generation. J. Electron. Test. 16(6): 575-589 (2000) - [j70]Avaneendra Gupta, John P. Hayes:
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. ACM Trans. Design Autom. Electr. Syst. 5(3): 510-547 (2000) - [j69]Ronald D. Blanton, John P. Hayes:
On the design of fast, easily testable ALU's. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 220-223 (2000) - [c51]Hussain Al-Asaad, John P. Hayes:
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. VTS 2000: 221-230
1990 – 1999
- 1999
- [j68]Mark C. Hansen, Hakan Yalcin, John P. Hayes:
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering. IEEE Des. Test Comput. 16(3): 72-80 (1999) - [c50]David Van Campenhout, Trevor N. Mudge, John P. Hayes:
High-Level Test Generation for Design Verification of Pipelined Microprocessors. DAC 1999: 185-188 - [c49]HyungWon Kim, John P. Hayes:
Delay fault testing of IP-based designs via symbolic path modeling. ITC 1999: 1045-1054 - [c48]Nagarajan Kandasamy, John P. Hayes, Brian T. Murray:
Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems. SRDS 1999: 212-221 - [c47]Avaneendra Gupta, John P. Hayes:
Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. VLSI Design 1999: 453-459 - [c46]HyungWon Kim, John P. Hayes:
Delay Fault Testing of Designs with Embedded IP Cores. VTS 1999: 160-167 - 1998
- [j67]Hussain Al-Asaad, Brian T. Murray, John P. Hayes:
Online BIST for Embedded Systems. IEEE Des. Test Comput. 15(4): 17-24 (1998) - [j66]Hussain Al-Asaad, John P. Hayes, Brian T. Murray:
Scalable Test Generators for High-Speed Datapath Circuits. J. Electron. Test. 12(1-2): 111-125 (1998) - [j65]Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes:
Optimal Zero-Aliasing Space Compaction of Test Responses. IEEE Trans. Computers 47(11): 1171-1187 (1998) - [j64]David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown:
High-level design verification of microprocessors via error modeling. ACM Trans. Design Autom. Electr. Syst. 3(4): 581-599 (1998) - [j63]Krishnendu Chakrabarty, John P. Hayes:
Zero-aliasing space compaction of test responses using multiple parity signatures. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 309-313 (1998) - [c45]Avaneendra Gupta, John P. Hayes:
Optimal 2-D cell layout with integrated transistor folding. ICCAD 1998: 128-135 - [c44]HyungWon Kim, John P. Hayes:
High-coverage ATPG for datapath circuits with unimplemented blocks. ITC 1998: 577-586 - 1997
- [j62]R. D. (Shawn) Blanton, John P. Hayes:
Testability Properties of Divergent Trees. J. Electron. Test. 11(3): 197-209 (1997) - [j61]Hung-Kuei Ku, John P. Hayes:
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses. IEEE Trans. Computers 46(4): 439-455 (1997) - [j60]Krishnendu Chakrabarty, John P. Hayes:
On the quality of accumulator-based compaction of test responses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 916-922 (1997) - [j59]Hakan Yalcin, John P. Hayes:
Event propagation conditions in circuit delay computation. ACM Trans. Design Autom. Electr. Syst. 2(3): 249-280 (1997) - [j58]Hung-Kuei Ku, John P. Hayes:
Connective Fault Tolerance in Multiple-Bus Systems. IEEE Trans. Parallel Distributed Syst. 8(6): 574-586 (1997) - [c43]Avaneendra Gupta, John P. Hayes:
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. DAC 1997: 452-455 - [c42]Ronald D. Blanton, John P. Hayes:
The input pattern fault model and its application. ED&TC 1997: 628 - [c41]Amit Chowdhary, John P. Hayes:
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. FPGA 1997: 43-49 - [c40]Ronald D. Blanton, John P. Hayes:
Properties of the Input Pattern Fault Model. ICCD 1997: 372-380 - [c39]Avaneendra Gupta, John P. Hayes:
A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. VLSI Design 1997: 15-20 - 1996
- [j57]Brian T. Murray, John P. Hayes:
Testing ICs: Getting to the Core of the Problem. Computer 29(11): 32-38 (1996) - [j56]Krishnendu Chakrabarty, John P. Hayes:
Balance testing and balance-testable design of logic circuits. J. Electron. Test. 8(1): 71-86 (1996) - [j55]Frank Harary, John P. Hayes:
Node fault tolerance in graphs. Networks 27(1): 19-23 (1996) - [j54]Hung-Kuei Ku, John P. Hayes:
Optimally edge fault-tolerant trees. Networks 27(3): 203-214 (1996) - [j53]Ronald D. Blanton, John P. Hayes:
Testability of Convergent Tree Circuits. IEEE Trans. Computers 45(8): 950-963 (1996) - [j52]Krishnendu Chakrabarty, John P. Hayes:
Test response compaction using multiplexed parity trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1399-1408 (1996) - [c38]Avaneendra Gupta, Siang-Chun The, John P. Hayes:
XPRESS: A Cell Layout Generator with Integrated Transistor Folding. ED&TC 1996: 393-401 - [c37]Hakan Yalcin, John P. Hayes, Karem A. Sakallah:
An approximate timing analysis method for datapath circuits. ICCAD 1996: 114-118 - [c36]Avaneendra Gupta, John P. Hayes:
Width minimization of two-dimensional CMOS cells using integer programming. ICCAD 1996: 660-667 - [c35]R. D. (Shawn) Blanton, John P. Hayes:
Design of a fast, easily testable ALU. VTS 1996: 9-16 - 1995
- [j51]Krishnendu Chakrabarty, John P. Hayes:
Cumulative balance testing of logic circuits. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 72-83 (1995) - [c34]Hussain Al-Asaad, John P. Hayes:
Design verification via simulation and automatic test pattern generation. ICCAD 1995: 174-180 - [c33]Amit Chowdhary, John P. Hayes:
Technology mapping for field-programmable gate arrays using integer programming. ICCAD 1995: 346-352 - [c32]Hakan Yalcin, John P. Hayes:
Hierarchical timing analysis using conditional delays. ICCAD 1995: 371-377 - [c31]Mark C. Hansen, John P. Hayes:
High-Level Test Generation Using Symbolic Scheduling. ITC 1995: 586-595 - [c30]Krishnendu Chakrabarty, Brian T. Murray, John P. Hayes:
Optimal Space Compaction of Test Responses. ITC 1995: 834-843 - [c29]Mark C. Hansen, John P. Hayes:
High-level test generation using physically-induced faults. VTS 1995: 20-28 - 1994
- [j50]Michael J. Batek, John P. Hayes:
Optimal Testing and Design of Adders. VLSI Design 1(4): 285-298 (1994) - [c28]Krishnendu Chakrabarty, John P. Hayes:
DFBT: A Design-for-Testability Method Based on Balance Testing. DAC 1994: 351-357 - [c27]Hung-Kuei Ku, John P. Hayes:
Connectivity and Fault Tolerance of Multiple-Bus Systems. FTCS 1994: 372-381 - [c26]Hung-Kuei Ku, John P. Hayes:
Structural fault tolerance in VLSI-based systems. Great Lakes Symposium on VLSI 1994: 50-55 - [c25]Krishnendu Chakrabarty, John P. Hayes:
Efficient Test-Response Compression for Multiple-Output Cicuits. ITC 1994: 501-510 - 1993
- [j49]Pinaki Mazumder, John P. Hayes:
Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories. IEEE Des. Test Comput. 10(1): 6-7 (1993) - [j48]Frank Harary, John P. Hayes:
Edge fault tolerance in graphs. Networks 23(2): 135-142 (1993) - [j47]Ram Raghavan, John P. Hayes:
Reducing Inerference Among Vector Accesses in Interleaved Memories. IEEE Trans. Computers 42(4): 471-483 (1993) - [c24]Ronald D. Blanton, John P. Hayes:
Efficient Testing of Tree Circuits. FTCS 1993: 176-185 - [c23]Krishnendu Chakrabarty, John P. Hayes:
Balance Testing of Logic Circuits. FTCS 1993: 350-359 - [c22]Krishnendu Chakrabarty, John P. Hayes:
Aliasing-free error detection (ALFRED). VTS 1993: 260-266 - 1992
- [j46]Tze Chiang Lee, John P. Hayes:
Design of Gracefully Degradable Hypercube-Connected Systems. J. Parallel Distributed Comput. 14(4): 390-401 (1992) - [j45]Shantanu Dutt, John P. Hayes:
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. IEEE Trans. Computers 41(5): 588-598 (1992) - [j44]Tze Chiang Lee, John P. Hayes:
A Fault-Tolerant Communication Scheme for Hypercube Computers. IEEE Trans. Computers 41(10): 1242-1256 (1992) - [j43]Eduard Cerny, John P. Hayes, Nicholas C. Rumin:
Accuracy of magnitude-class calculations in switch-level modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4): 443-452 (1992) - [c21]Michael J. Batek, John P. Hayes:
Test-Set Preserving Logic Transformations. DAC 1992: 454-458 - 1991
- [j42]Shantanu Dutt, John P. Hayes:
Designing Fault-Tolerant System Using Automorphisms. J. Parallel Distributed Comput. 12(3): 249-268 (1991) - [j41]Shantanu Dutt, John P. Hayes:
Subcube Allocation in Hypercube Computers. IEEE Trans. Computers 40(3): 341-352 (1991) - [c20]Robert L. Maziasz, John P. Hayes:
Exact Width and Height Minimization of CMOS Cells. DAC 1991: 487-493 - [c19]Shantanu Dutt, John P. Hayes:
Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. FTCS 1991: 292-299 - [c18]Ram Raghavan, John P. Hayes:
Scalar-Vector Memory Interference in Vector Computers. ICPP (1) 1991: 180-187 - [c17]Brian T. Murray, John P. Hayes:
Test Propagation Through Modules and Circuits. ITC 1991: 748-757 - 1990
- [j40]Debashis Bhattacharya, John P. Hayes:
A hierarchical test generation methodology for digital circuits. J. Electron. Test. 1(2): 103-123 (1990) - [j39]Shantanu Dutt, John P. Hayes:
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. IEEE Trans. Computers 39(4): 490-503 (1990) - [j38]Brian T. Murray, John P. Hayes:
Hierarchical test generation using precomputed tests for modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 594-603 (1990) - [j37]Robert L. Maziasz, John P. Hayes:
Layout optimization of static CMOS functional cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 708-719 (1990) - [j36]Debashis Bhattacharya, John P. Hayes:
Designing for high-level test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 752-766 (1990) - [c16]Ram Raghavan, John P. Hayes:
On randomly interleaved memories. SC 1990: 49-58
1980 – 1989
- 1989
- [j35]Debashis Bhattacharya, Brian T. Murray, John P. Hayes:
High-Level Test Generation for VLSI. Computer 22(4): 16-24 (1989) - [j34]John P. Hayes, Trevor N. Mudge:
Hypercube supercomputers. Proc. IEEE 77(12): 1829-1841 (1989) - [c15]Shantanu Dutt, John P. Hayes:
An automorphic approach to the design of fault-tolerant multiprocessors. FTCS 1989: 496-503 - [c14]Eduard Cerny, John P. Hayes, Nicholas C. Rumin:
Magnitude classes in switch-level modeling. ICCD 1989: 284-288 - 1988
- [j33]Raif M. Yanney, John P. Hayes:
Fault Recovery in Distributed Processing Loop Networks. Comput. Networks 15: 229-243 (1988) - [j32]Musaravakkam S. Krishnan, John P. Hayes:
A normalized-area measure for VLSI layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 411-419 (1988) - [j31]Y. You, John P. Hayes:
Implementation of VLSI self-testing by regularization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12): 1261-1271 (1988) - [c13]Tze Chiang Lee, John P. Hayes:
Routing and broadcasting in faulty hypercube computers. C³P 1988: 346-354 - [c12]Shantanu Dutt, John P. Hayes:
On allocating subcubes in a hypercube multiprocessor. C³P 1988: 801-810 - [c11]Shantanu Dutt, John P. Hayes:
Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures. FTCS 1988: 328-333 - [c10]Ram Raghavan, John P. Hayes, William R. Martin:
Logic simulation on vector processors. ICCAD 1988: 268-271 - [c9]Brian T. Murray, John P. Hayes:
Hierarchical Test Generation Using Precomputed Tests for Modules. ITC 1988: 221-229 - 1987
- [j30]Trevor N. Mudge, John P. Hayes, Donald C. Winsor:
Multiple Bus Architectures. Computer 20(6): 42-48 (1987) - [j29]John P. Hayes:
An Introduction to Switch-Level Modeling. IEEE Des. Test 4(4): 18-25 (1987) - [c8]R. L. Maiasz, John P. Hayes:
Layout Optimization of CMOS Functional Cells. DAC 1987: 544-551 - 1986
- [j28]Trevor N. Mudge, John P. Hayes, Gregory D. Buzzard, Donald C. Winsor:
Analysis of Multiple-Bus Interconnection Networks. J. Parallel Distributed Comput. 3(3): 328-343 (1986) - [j27]John P. Hayes, Trevor N. Mudge, Quentin F. Stout, Stephen Colley, John Palmer:
A Microprocessor-based Hypercube Supercomputer. IEEE Micro 6(5): 6-17 (1986) - [j26]John Paul Shen, John P. Hayes, Luigi Ciminiera, Angelo Serra:
Fault-tolerance and performance analysis of beta-networks. Parallel Comput. 3(3): 231-249 (1986) - [j25]John P. Hayes:
Uncertainty, Energy, and Multiple-Valued Logics. IEEE Trans. Computers 35(2): 107-114 (1986) - [j24]John P. Hayes:
Pseudo-Boolean Logic Circuits. IEEE Trans. Computers 35(7): 602-612 (1986) - [j23]Raif M. Yanney, John P. Hayes:
Distributed Recovery in Fault-Tolerant Multiprocessor Networks. IEEE Trans. Computers 35(10): 871-879 (1986) - [j22]Musaravakkam S. Krishnan, John P. Hayes:
An Array Layout Methodology for VLlSI Circuits. IEEE Trans. Computers 35(12): 1055-1067 (1986) - [j21]John P. Hayes:
Digital Simulation with Multiple Logic Values. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(2): 274-283 (1986) - [c7]John P. Hayes, Trevor N. Mudge, Quentin F. Stout:
Architecture of a Hypercube Supercomputer. ICPP 1986: 653-660 - 1984
- [j20]John Paul Shen, John P. Hayes:
Fault-Tolerance of Dynamic-Full-Access Interconnection Networks. IEEE Trans. Computers 33(3): 241-248 (1984) - [j19]John P. Hayes:
Fault Modeling for Digital MOS Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3): 200-208 (1984) - [c6]Masato Kawai, John P. Hayes:
An experimental MOS fault simulation program CSASIM. DAC 1984: 2-9 - [c5]Raif M. Yanney, John P. Hayes:
Distributed Recovery in Fault-Tolerant Multiprocessor Networks. ICDCS 1984: 514-525 - 1982
- [c4]John P. Hayes:
A fault simulation methodology for VLSI. DAC 1982: 393-399 - 1981
- [j18]Thirumalai Sridhar, John P. Hayes:
A Functional Approach to Testing Bit-Sliced Microprocessors. IEEE Trans. Computers 30(8): 563-571 (1981) - [j17]Thirumalai Sridhar, John P. Hayes:
Design of Easily Testable Bit-Sliced Systems. IEEE Trans. Computers 30(11): 842-854 (1981) - 1980
- [j16]John P. Hayes, Edward J. McCluskey:
Testability Considerotions in Microprocessor-Based Design. Computer 13(3): 17-26 (1980) - [j15]Ayee Goundan, John P. Hayes:
Design of Totally Fault Locatable Combinational Networks. IEEE Trans. Computers 29(1): 33-44 (1980) - [j14]John P. Hayes:
Testing Memories for Single-Cell Pattern-Sensitive Faults. IEEE Trans. Computers 29(3): 249-254 (1980) - [j13]Ayee Goundan, John P. Hayes:
Identification of Equivalent Faults in Logic Networks. IEEE Trans. Computers 29(11): 978-985 (1980) - [c3]John Paul Shen, John P. Hayes:
Fault Tolerance of a Class of Connecting Networks. ISCA 1980: 61-71
1970 – 1979
- 1978
- [j12]John P. Hayes:
Generation of Optimal Transition Count Tests. IEEE Trans. Computers 27(1): 36-41 (1978) - [j11]John P. Hayes:
Path Complexity of Logic Networks. IEEE Trans. Computers 27(5): 459-462 (1978) - 1976
- [j10]John P. Hayes:
Enumeration of Fanout-Free Boolean Functions. J. ACM 23(4): 700-709 (1976) - [j9]John P. Hayes:
Transition Count Testing of Combinational Logic Circuits. IEEE Trans. Computers 25(6): 613-620 (1976) - [j8]John P. Hayes:
A Graph Model for Fault-Tolerant Computing Systems. IEEE Trans. Computers 25(9): 875-884 (1976) - [j7]John P. Hayes:
On the Properties of Irredundant Logic Networks. IEEE Trans. Computers 25(9): 884-892 (1976) - [c2]Ayee Goundan, John P. Hayes:
Partitioning logic circuits to maximize fault resolution. DAC 1976: 271-277 - 1975
- [j6]John P. Hayes:
The Fanout Structure of Switching Functions. J. ACM 22(4): 551-571 (1975) - [j5]John P. Hayes:
Detection of Pattern-Sensitive Faults in Random-Access Memories. IEEE Trans. Computers 24(2): 150-157 (1975) - 1974
- [j4]John P. Hayes:
On Modifying Logic Networks to Improve Their Diagnosability. IEEE Trans. Computers 23(1): 56-62 (1974) - [j3]John P. Hayes, Arthur D. Friedman:
Test Point Placement to Simplify Fault Detection. IEEE Trans. Computers 23(7): 727-735 (1974) - [c1]John P. Hayes:
Minimization of Fanout in Switching Networks. SWAT 1974: 133-139 - 1971
- [j2]John P. Hayes:
A Nand Model ror Fault Diagnosis in Combinational Logic Networks. IEEE Trans. Computers 20(12): 1496-1506 (1971) - [j1]John P. Hayes:
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests. IEEE Trans. Computers 20(12): 1506-1513 (1971) - 1970
- [b1]John Patrick Hayes:
A Study of Digital Network Structure and Its Relation to Fault Diagnosis. University of Illinois Urbana-Champaign, USA, 1970
Coauthor Index
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