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ORCIDRes Saleh
Resve A. Saleh – Resve Aslam Saleh
Person information
- affiliation: University of British Columbia, Department of Electrical and Computer Engineering, Vancouver, BC, Canada
- affiliation: Simplex Solutions, Sunnyvale, CA, USA
- affiliation: University of Illinois, Department of Electrical and Computer Engineering, Urbana, IL, USA
- affiliation (PhD 1986): University of California, Berkeley, CA, USA
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2020 – today
- 2022
[j28]Sohaib Majzoub
, Resve A. Saleh, Mottaqiallah Taouil, Said Hamdioui, Mohamed Bamakhrama:
Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning. IEEE Access 10: 70187-70203 (2022)- [i2]Resve A. Saleh, A. K. Md. Ehsanes Saleh:
Statistical Properties of the log-cosh Loss Function Used in Machine Learning. CoRR abs/2208.04564 (2022) - 2021
- [i1]Resve A. Saleh, A. K. Md. Ehsanes Saleh:
Solution to the Non-Monotonicity and Crossing Problems in Quantile Regression. CoRR abs/2111.04805 (2021)
2010 – 2019
- 2019
- [j27]Sohaib Majzoub, Resve A. Saleh, Imran Ashraf, Mottaqiallah Taouil, Said Hamdioui:
Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era. IEEE Access 7: 33115-33129 (2019) - 2011
- [j26]Jeffrey G. Mueller, Resve A. Saleh:
Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 973-986 (2011) - [c52]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh:
Sequence pair based voltage island floorplanning. IGCC 2011: 1-6 - [c51]Tatsuya Koyagi, Sohaib Majzoub, Masahiro Fukui, Resve A. Saleh:
RTL delay macro-modeling with Vt and Vdd variability. IDT 2011: 118-123 - [c50]Arash Zargaran-Yazd, Shahriar Mirabbasi, Res Saleh:
A 10 Gb/s low-power serdes receiver based on a hybrid speculative/SAR digitization technique. ISCAS 2011: 446-449 - 2010
- [j25]Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab K. Ward:
Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 816-829 (2010)
2000 – 2009
- 2009
- [j24]Xiongfei Meng, Resve A. Saleh:
An Improved Active Decoupling Capacitor for "Hot-Spot" Supply Noise Reduction in ASIC Designs. IEEE J. Solid State Circuits 44(2): 584-593 (2009) - [j23]Dipanjan Sengupta, Resve A. Saleh:
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 316-326 (2009) - [c49]Xiongfei Meng, Resve A. Saleh, Steven J. E. Wilton:
Charge-borrowing decap: A novel circuit for removal of local supply noise violations. CICC 2009: 25-28 - [c48]Xiongfei Meng, Resve A. Saleh:
Active decap design considerations for optimal supply noise reduction. ISQED 2009: 765-769 - [c47]Sohaib Majzoub, Resve A. Saleh, Rabab K. Ward:
PVT variation impact on voltage island formation in MPSoC design. ISQED 2009: 814-819 - [c46]Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Ward:
Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms. SoC 2009: 1-4 - [c45]Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward:
Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. SoCC 2009: 357-360 - 2008
- [j22]Peter Hallschmid, Resve A. Saleh:
Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 508-515 (2008) - [j21]Zahra Sadat Ebadi, Resve A. Saleh:
Adaptive Compensation of RF Front-End Nonidealities in Direct Conversion Receivers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(4): 354-358 (2008) - [j20]Xiongfei Meng, Resve A. Saleh, Karim Arabi:
Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1581-1588 (2008) - [c44]Dipanjan Sengupta, Resve A. Saleh:
Application-driven floorplan-aware voltage island design. DAC 2008: 155-160 - [c43]Tatsuya Koyagi, Masahiro Fukui, Resve A. Saleh:
Delay macromodeling and estimation for RTL. ISCAS 2008: 2430-2433 - [c42]Zahra Sadat Ebadi, Resve A. Saleh:
A Fully-Integrated 2.4 GHz Mismatch-Controllable RF Front-end Test Platform in 0.18µm CMOS. ISQED 2008: 411-416 - [c41]Jeff Mueller, Resve A. Saleh:
A Tunable Clock Buffer for Intra-die PVT Compensation in Single-Edge Clock (SEC) Distribution Networks. ISQED 2008: 572-577 - [c40]Uthman Alsaiari, Resve A. Saleh:
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. ISQED 2008: 798-803 - [c39]Dipanjan Sengupta, Resve A. Saleh:
Supply voltage selection in Voltage Island based SoC design. SoCC 2008: 219-222 - [c38]Jeff Mueller, Resve A. Saleh:
Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance. VLSI Design 2008: 214-219 - 2007
- [j19]Karim Arabi, Resve A. Saleh, Xiongfei Meng:
Power Supply Noise in SoCs: Metrics, Management, and Measurement. IEEE Des. Test Comput. 24(3): 236-244 (2007) - [j18]Zahra Sadat Ebadi, Alireza Nasiri Avanaki, Resve A. Saleh, André Ivanov:
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip. Integr. 40(2): 149-160 (2007) - [j17]Dipanjan Sengupta, Resve A. Saleh:
Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 183-189 (2007) - [j16]Cristian Grecu, André Ivanov, Resve A. Saleh, Partha Pratim Pande:
Testing Network-on-Chip Communication Fabrics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2201-2214 (2007) - [c37]Peter Hallschmid, Resve A. Saleh:
Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. DAC 2007: 732-737 - [c36]Cristian Grecu, Lorena Anghel, Partha Pratim Pande, André Ivanov, Resve A. Saleh:
Essential Fault-Tolerance Metrics for NoC Infrastructures. IOLTS 2007: 37-42 - [c35]Xiongfei Meng, Karim Arabi, Resve A. Saleh:
A Novel Active Decoupling Capacitor Design in 90nm CMOS. ISCAS 2007: 657-660 - [c34]Amit Kedia, Resve A. Saleh:
Power Reduction of On-Chip Serial Links. ISCAS 2007: 865-868 - [c33]Resve A. Saleh, Pallab K. Chatterjee, Ivan Pesic, Robbert Dobkins, Mike Smayling, Joseph Sawicki:
DFM-EDA's Salvation or its Excuse for Being out of Touch with Engineering? ISQED 2007: 7-8 - [c32]Uthman Alsaiari, Resve A. Saleh:
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. ISQED 2007: 703-710 - 2006
- [j15]Resve A. Saleh, Steven J. E. Wilton, Shahriar Mirabbasi, Alan J. Hu, Mark R. Greenstreet, Guy Lemieux, Partha Pratim Pande, Cristian Grecu, André Ivanov:
System-on-Chip: Reuse and Integration. Proc. IEEE 94(6): 1050-1069 (2006) - [j14]Zahra Sadat Ebadi, Shahriar Mirabbasi, Resve A. Saleh:
The application of complex quantized feedback in integrated wireless receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(3): 594-603 (2006) - [c31]Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande:
NoC Interconnect Yield Improvement Using Crosspoint Redundancy. DFT 2006: 457-465 - [c30]Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande:
On-line Fault Detection and Location for NoC Interconnects. IOLTS 2006: 145-150 - [c29]Uthman Alsaiari, Resve A. Saleh:
Testable and self-repairable structured logic design. ISCAS 2006 - [c28]Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh:
A high-speed low-energy dynamic PLA using an input-isolation scheme. ISCAS 2006 - [c27]Xiongfei Meng, Resve A. Saleh, Karim Arabi:
Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology. ISQED 2006: 266-271 - [c26]Victor O. Aken'Ova, Resve A. Saleh:
A "Soft++" eFPGA Physical Design Approach with Case Studies in 180nm and 90nm. ISVLSI 2006: 103-108 - [c25]Peter Hallschmid, Resve A. Saleh:
Fast Configuration of an Energy-Efficient Branch Predictor. ISVLSI 2006: 289-294 - [c24]Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh:
BIST for Network-on-Chip Interconnect Infrastructures. VTS 2006: 30-35 - 2005
- [j13]Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli:
Design, Synthesis, and Test of Networks on Chips. IEEE Des. Test Comput. 22(5): 404-413 (2005) - [j12]Resve A. Saleh:
An approach that will NoC your SoCs off! IEEE Des. Test Comput. 22(5): 488 (2005) - [j11]Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh:
Timing analysis of network on chip architectures for MP-SoC platforms. Microelectron. J. 36(9): 833-845 (2005) - [j10]Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh:
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. IEEE Trans. Computers 54(8): 1025-1040 (2005) - [c23]Victor O. Aken'Ova, Guy Lemieux, Resve A. Saleh:
An improved "soft" eFPGA design and implementation strategy. CICC 2005: 179-182 - [c22]Cristian Grecu, Partha Pratim Pande, Baosheng Wang, André Ivanov, Res Saleh:
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects. DFT 2005: 238-246 - [c21]Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh:
Effect of traffic localization on energy dissipation in NoC-based interconnect. ISCAS (2) 2005: 1774-1777 - [c20]Dipanjan Sengupta, Resve A. Saleh:
Power-Delay Metrics Revisited for 90nm CMOS Technology. ISQED 2005: 291-296 - 2004
- [c19]Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh:
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. ACM Great Lakes Symposium on VLSI 2004: 192-195 - [c18]Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh:
A Scalable Communication-Centric SoC Interconnect Architecture. ISQED 2004: 343-348 - 2003
- [c17]James C. H. Wu, Victor O. Aken'Ova, Steven J. E. Wilton, Resve A. Saleh:
SoC implementation issues for synthesizable embedded programmable logic cores. CICC 2003: 45-48 - [c16]Stephan Shang, Shahriar Mirabbasi, Resve A. Saleh:
A technique for DC-offset removal and carrier phase error compensation in integrated wireless receivers. ISCAS (1) 2003: 173-176 - [c15]Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh:
Design of a switch for network on chip applications. ISCAS (5) 2003: 217-220 - [c14]Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov:
Analog IP design flow for SoC applications. ISCAS (4) 2003: 676-679 - 2002
- [c13]Resve A. Saleh, G. Lim, T. Kadowaki, K. Uchiyama:
Trends in Low Power Digital System-on-Chip Designs (invited). ISQED 2002: 373-378 - [c12]Mohsen Nahvi, André Ivanov, Resve A. Saleh:
Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores. ITC 2002: 1176-1184 - 2000
- [j9]Resve A. Saleh, Syed Zakir Hussain, Steffen Rochel, David Overhauser:
Clock skew verification in the presence of IR-drop in the powerdistribution network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6): 635-644 (2000)
1990 – 1999
- 1998
- [c11]Resve A. Saleh, David Overhauser, Sandy Taylor:
Full-chip verification of UDSM designs. ICCAD 1998: 453-460 - 1996
- [j8]Resve A. Saleh, Brian A. A. Antao, Jaidip Singh:
Multilevel and mixed-domain simulation of analog circuits and systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 68-82 (1996) - [j7]Jeffrey G. Mueller, Brian A. A. Antao, Resve A. Saleh:
A multifrequency technique for frequency response computation with application to switched-capacitor circuits with nonlinearities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 775-790 (1996) - 1995
- [c10]Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh:
Improving Parallel Circuit Simulation Using High-Level Waveforms. ISCAS 1995: 728-731 - 1994
- [b1]Resve A. Saleh, Shyh-Jye Jou, A. Richard Newton:
Mixed-mode simulation and analog multilevel simulation. The Kluwer international series in engineering and computer science, Kluwer 1994, ISBN 978-0-7923-9473-0, pp. I-XI, 1-302 - 1993
- [j6]Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh:
Improving the performance of parallel relaxation-based circuit simulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11): 1762-1774 (1993) - 1992
- [j5]Eugene Z. Xia, Resve A. Saleh:
Parallel waveform-Newton algorithms for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4): 432-442 (1992) - [c9]Yun-Cheng Ju, Resve A. Saleh:
Incremental Circuit Simulation Using Waveform Relaxation. DAC 1992: 8-11 - [c8]Ken Kubiak, Steven Parkes, W. Kent Fuchs, Resve A. Saleh:
Exact Evaluation of Diagnostic Test Resolution. DAC 1992: 347-352 - 1991
- [j4]Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh:
Consistency checking and optimization of macromodels. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 957-967 (1991) - [c7]Yun-Cheng Ju, Resve A. Saleh:
Incremental Techniques for the Identification of Statically Sensitizable Critical Paths. DAC 1991: 541-546 - [c6]Jaidip Singh, Resve A. Saleh:
iMACSIM: A Program for Multi-Level Analog Circuit Simulation. ICCAD 1991: 16-19 - [c5]Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh:
Parallel Event-Driven Waveform Relaxation. ICCD 1991: 101-104 - [c4]Yun-Cheng Ju, Resve A. Saleh:
Identification of Viable Paths Using Binary Decision Diagrams. ICCD 1991: 638-641 - 1990
- [j3]Eduardo L. Acuna, James P. Dervenis, Andrew J. Pagones, Fred L. Yang, Resve A. Saleh:
Simulation techniques for mixed analog/digital circuits. IEEE J. Solid State Circuits 25(2): 353-363 (1990) - [j2]Resve A. Saleh, Jacob K. White:
Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 951-958 (1990) - [c3]Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh:
Parallel Circuit Simulation Using Hierarchical Relaxation. DAC 1990: 394-399 - [c2]Yun-Cheng Ju, Fred L. Yang, Resve A. Saleh:
Mixed-Mode Incremental Simulation and Concurrent Fault Simulation. ICCAD 1990: 158-161
1980 – 1989
- 1989
- [j1]Resve A. Saleh, A. Richard Newton:
The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12): 1286-1298 (1989) - 1988
- [c1]Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh:
Compaction of ATPG-generated test sequences for sequential circuits. ICCAD 1988: 382-385
Coauthor Index
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