Article

Free access

A framework for industrial layout generators

Authors:

Wayne Bower,

Carl Seaquist,

Wayne WolfAuthors Info & Claims

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

Pages 419 - 424

https://doi.org/10.1145/123186.123322

Published: 03 January 1991 Publication History

PDF eReader

Abstract

The MACLOG layout generator set is built on an object-oriented framework. Most frameworks are built around the hierarchy of module types. We found the service hierarchy—the types of information provided to the user by the generator—made the framework and generators easier to design and modify. This paper describes the MACLOG framework and details our experience with framework structure.

References

[1]

Bjarne Stroustrup. The C++ Programming Language. Addison-Wesley, Reading MA, 1986.

Digital Library

Google Scholar

[2]

Chris Kingsley. A hierarchical, error-tolerant compactor. In Proceedings, 21"t Design Automation Conference, pages 293-297, ACM/IEEE, 3une 1984.

Digital Library

Google Scholar

[3]

Richard J. Lipton, Stephen C. North, Jacobo Valdes, Gopalakrishnan Vijiyan, and Robert Sedgewick. VLSI layout as programming. ACM Tram'actions on Programming Languages and Systems, 5(3):405- 421, 1983.

Digital Library

Google Scholar

[4]

"Ibm Davis and Jim Clark. SILT: A VLSI Design language. Technical Report, Stanford University, June 1983.

Google Scholar

[5]

S. C. Johnson and S. A. Browning. The LSI design language i. 1980. Bell Laboratories Internal Memorandum.

Google Scholar

[6]

Dwight Hill, Don Shugard, John Fishb~ma, and Kurt Keutzer. Algorithms and Techniques for VLSI Layout Synthesis. Kluwer Academic Publishers, Boston MA, 1989.

Digital Library

Google Scholar

[7]

John Batali and Anne Hartheimer. The Design Procedure Language manual. Technical Report 598, MIT AI Lab, September 1980.

Google Scholar

[8]

John Batali, Neil Mayle, Howard $1trobe, Gerald Sussman, and Daniel Weise. The DPL/Daealalus design environment. In John P. Gray, editor, VLSI 81, pages 183-192, Academic Press, 1981.

Google Scholar

[9]

Harold Brown, Christopher Tong, and Gordon Foyster. Palladio: an exploratory environment for circuit design. In Computer, pages 41-56, IEEE Computer Society, December 1983.

Google Scholar

[10]

Wayne Wolf. How to build a hardware description and measurement system on an object-oriented programming language. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8(3):288-301, March 1989.

Crossref

Google Scholar

[11]

William D. Smith, Jeffrey R. Jasica, Michael J. Hartman, and Manuel A. d'Abreau. Flexible module generation in the FACE design environment. In Proceedings, ICCAD-88, pages 396-399, IEEE Computer Society Press, 1988.

Google Scholar

[12]

W. D. Smith, D. Duff, M. Dragomirecky, J. Caldwell, M. Hartman, 1. Jasica, and M. A. d'Abreu. FACE Core Environment: the model and its application in CAE/CAD tool development. In Proceedings, 26th Design Automation Conference, pages 466--471, ACM/IEEE, June 1989.

Digital Library

Google Scholar

Cited By

View all

Tyagi A(1993)A Module Generator Development Environment: Area Estimation and Design-Space Exploration EncapsulationThe Sixth International Conference on VLSI Design10.1109/ICVD.1993.669681(214-217)Online publication date: 1993
https://doi.org/10.1109/ICVD.1993.669681
Beetem J(1992)Rapid implementation of hierarchical integrated simulators using Galaxy[1991 Proceedings] The Second International Workshop on Rapid System Prototyping10.1109/IWRSP.1991.218611(181-199)Online publication date: 1992
https://doi.org/10.1109/IWRSP.1991.218611

Index Terms

A framework for industrial layout generators
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning

Recommendations

A framework for industrial layout generators

The MACLOG family of layout generators creates parameterized custom layouts for many of the cells in the AT&T Cell Library. The authors describe not the MACLOG generators themselves, but the MACLOG framework that is the base of all the generators. The ...
Bit-Wise Behavior of Random Number Generators

In 1985, G. Marsaglia proposed the m-tuple test, a runs test on bits, as a test of nonrandomness of a sequence of pseudorandom integers. We try this test on the outputs from a large set of pseudorandom number generators and discuss the behavior of the ...
Paradigms for Unconditional Pseudorandom Generators

This is a survey of unconditional pseudorandom generators (PRGs). A PRG uses a short, truly random seed to generate a long, "pseudorandom" sequence of bits. To be more specific, for each restricted model of computation (e.g., bounded-depth circuits or ...

Comments

Information & Contributors

Information

Published In

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

January 1991

742 pages

ISBN:0897913639

DOI:10.1145/123186

Chairman:
Richard C. Smith

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 January 1991

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC90

Sponsor:

SIGDA
IEEE-CS

DAC90: The 27th ACM/IEEE-CS Design Automation Conference

June 24 - 27, 1990

Florida, Orlando, USA

Acceptance Rates

DAC '90 Paper Acceptance Rate 125 of 427 submissions, 29%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
244
Total Downloads

Downloads (Last 12 months)16
Downloads (Last 6 weeks)1

Reflects downloads up to 09 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Tyagi A(1993)A Module Generator Development Environment: Area Estimation and Design-Space Exploration EncapsulationThe Sixth International Conference on VLSI Design10.1109/ICVD.1993.669681(214-217)Online publication date: 1993
https://doi.org/10.1109/ICVD.1993.669681
Beetem J(1992)Rapid implementation of hierarchical integrated simulators using Galaxy[1991 Proceedings] The Second International Workshop on Rapid System Prototyping10.1109/IWRSP.1991.218611(181-199)Online publication date: 1992
https://doi.org/10.1109/IWRSP.1991.218611

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations