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ORCIDChirayu S. Amin
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2010 – 2019
- 2014
[c14]Parijat Mukherjee, Chirayu S. Amin, Peng Li:
Approximate property checking of mixed-signal circuits. DAC 2014: 115:1-115:6
2000 – 2009
- 2008
- [c13]Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin:
A "true" electrical cell model for timing, noise, and power grid verification. DAC 2008: 462-467 - [c12]Chandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin:
Silicon feedback to improve frequency of high-performance microprocessors: an overview. ICCAD 2008: 778-782 - 2007
- [c11]Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout:
A nonlinear cell macromodel for digital applications. ICCAD 2007: 678-685 - 2006
- [c10]Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout:
A multi-port current source model for multiple-input switching effects in CMOS library cells. DAC 2006: 247-252 - 2005
- [j3]Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail:
Realizable reduction of interconnect circuits including self and mutual inductances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 271-277 (2005) - [j2]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Weibull-based analytical waveform model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1156-1168 (2005) - [c9]Chirayu S. Amin, Noel Menezes, Kip Killpack, Florentin Dartu, Umakanta Choudhury, Nagib Hakim, Yehea I. Ismail:
Statistical static timing analysis: how simple can we get? DAC 2005: 652-657 - [c8]Chirayu S. Amin, Yehea I. Ismail, Florentin Dartu:
Piece-wise approximations of RLCK circuit responses using moment matching. DAC 2005: 927-932 - [c7]Ahmed M. Shebaita, Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Expanding the frequency range of AWE via time shifting. ICCAD 2005: 935-938 - 2004
- [j1]Yehea I. Ismail, Chirayu S. Amin:
Computation of signal-threshold crossing times directly from higher order moments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1264-1276 (2004) - [c6]Yehea I. Ismail, Chirayu S. Amin:
Computation of signal threshold crossing times directly from higher order moments. ICCAD 2004: 246-253 - [c5]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Modeling unbuffered latches for timing analysis. ICCAD 2004: 254-260 - 2003
- [c4]Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail:
Realizable RLCK circuit crunching. DAC 2003: 226-231 - [c3]Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail:
Efficient model order reduction including skin effect. DAC 2003: 232-237 - [c2]Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail:
Weibull Based Analytical Waveform Model. ICCAD 2003: 161-168 - [c1]Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter:
Realizable reduction of RLC circuits using node elimination. ISCAS (3) 2003: 494-497
Coauthor Index
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