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ORCIDMasud H. Chowdhury
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- affiliation: University of Illinois at Chicago, USA
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2020 – today
- 2022
[j26]Zarin Tasnim Sandhie
, Jill Arvindbhai Patel, Farid Uddin Ahmed, Masud H. Chowdhury:
Investigation of Multiple-valued Logic Technologies for Beyond-binary Era. ACM Comput. Surv. 54(1): 16:1-16:30 (2022)- [j25]Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury:
Design of novel 3T ternary DRAM with single word-line using CNTFET. Microelectron. J. 126: 105498 (2022) - 2021
- [j24]Farid Uddin Ahmed, Zarin Tasnim Sandhie, Liaquat Ali, Masud H. Chowdhury:
A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits. IEEE Access 9: 813-826 (2021) - [j23]Mahmood Uddin Mohammed, Athiya Nizam, Liaquat Ali, Masud H. Chowdhury:
FinFET based SRAMs in Sub-10nm domain. Microelectron. J. 114: 105116 (2021) - [j22]Karthikeyan Nagarajan, Farid Uddin Ahmed, Mohammad Nasim Imtiaz Khan, Asmit De, Masud H. Chowdhury, Swaroop Ghosh:
SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1518-1528 (2021) - [i2]Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury:
Design of Novel 3T Ternary DRAM with Single Word-Line using CNTFET. CoRR abs/2108.09342 (2021) - 2020
- [c96]Farid Uddin Ahmed, Zarin Tasnim Sandhie, Masud H. Chowdhury:
An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V. ICCD 2020: 453-456 - [c95]Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury:
GNRFET based Ternary Logic - Prospects and Potential Implementation. LASCAS 2020: 1-4 - [c94]Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury:
Design of Ternary Master-Slave D-Flip Flop using MOS-GNRFET. MWSCAS 2020: 554-557
2010 – 2019
- 2019
- [c93]Mahmood Uddin Mohammed, Masud H. Chowdhury:
Design of Energy Efficient SRAM Cell Based on Double Gate Schottky-Barrier-Type GNRFET with Minimum Dimer Lines. ISCAS 2019: 1-4 - [c92]Mahmood Uddin Mohammed, Athiya Nizam, Liaquat Ali, Masud H. Chowdhury:
A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET. ISCAS 2019: 1-4 - 2018
- [j21]Emeshaw Ashenafi, Abdul Hamid Bin Yousuf, Masud H. Chowdhury:
Investigation and Optimization of Spiral Inductor Design for On-Chip Buck Converter. J. Low Power Electron. 14(1): 57-66 (2018) - [j20]Emeshaw Ashenafi, Masud H. Chowdhury:
A New Power Gating Circuit Design Approach Using Double-Gate FDSOI. IEEE Trans. Circuits Syst. II Express Briefs 65-II(8): 1074-1078 (2018) - [j19]Mahmood Uddin Mohammed, Masud H. Chowdhury:
Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1829-1833 (2018) - [c91]Nahid M. Hossain, Ritesh Kumar Reddy Kuchukulla, Masud H. Chowdhury:
Failure Analysis of the Through Silicon Via in Three-dimensional Integrated Circuit (3D-IC). ISCAS 2018: 1-4 - [c90]Marouf Khan, Masud H. Chowdhury:
Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate. ISCAS 2018: 1-5 - [c89]Mahmood Uddin Mohammed, Nahid M. Hossain, Masud H. Chowdhury:
A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme. MWSCAS 2018: 412-415 - [c88]Mahmood Uddin Mohammed, Rakesh Vijjapuram, Masud H. Chowdhury:
Novel CNTFET and Memristor based Unbalanced Ternary Logic Gate. MWSCAS 2018: 1106-1109 - [c87]Farid Uddin Ahmed, Masud H. Chowdhury:
An Asynchronous Reconfigurable Switched Capacitor Voltage Regulator. MWSCAS 2018: 1110-1113 - [c86]Jill Arvindbhai Patel, Zarin Tasnim Sandhie, Masud H. Chowdhury:
Ternary Device using Graphene Memcapacitor for Post Binary Era. MWSCAS 2018: 1130-1133 - 2017
- [j18]Abdullah G. Alharbi, Mohammed E. Fouda, Zainulabideen J. Khalifa, Masud H. Chowdhury:
Electrical Nonlinearity Emulation Technique for Current-Controlled Memristive Devices. IEEE Access 5: 5399-5409 (2017) - [j17]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET. Microelectron. J. 62: 30-37 (2017) - [j16]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j15]Muhammad Sanaullah, Masud H. Chowdhury:
Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1831-1841 (2017) - [c85]Muhammad Sana Ullah, Abdullah G. Alharbi, Masud H. Chowdhury:
BPSK modulation based exact BER computation for network intra-chip RF interconnect. ICM 2017: 1-4 - [c84]Emeshaw Ashenafi, Masud H. Chowdhury:
Noise voltage analysis of spiral inductor for on-chip buck converter design. ISCAS 2017: 1-4 - [c83]Emeshaw Ashenafi, Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Nodal thermal analysis for multi-VT SOFFET based subthreshold circuits. ISCAS 2017: 1-4 - [c82]Abdul Hamid Bin Yousuf, Nahid M. Hossain, Masud H. Chowdhury:
Impacts of different shapes of through-silicon-via core on 3D IC performance. ISCAS 2017: 1-4 - [c81]Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury:
Error free sense amplifier circuit design for STT-MRAM nonvolatile memory. MWSCAS 2017: 703-706 - [c80]Lohith Kumar Vemula, Nahid M. Hossain, Masud H. Chowdhury:
Emerging STT-MRAM circuit and architecture co-design in 45nm technology. MWSCAS 2017: 719-722 - [c79]Muhammad Sana Ullah, Masud H. Chowdhury:
Optimization of subthreshold swing for multilayer MoS2 tunnel transistor. MWSCAS 2017: 981-984 - [c78]Nahid M. Hossain, Emeshaw Ashenafi, Moqbull Hossen, Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Multilayer graphene nanoribbon based BioFET sensor design. MWSCAS 2017: 1402-1405 - [c77]Nahid M. Hossain, Arif Iqbal, Hemanshu Shishupal, Masud H. Chowdhury:
Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain. MWSCAS 2017: 1485-1488 - 2016
- [j14]MunEm Hossain, Masud H. Chowdhury:
Comprehensive doping scheme for MOSFETs in ultra-low-power subthreshold circuits design. Microelectron. J. 52: 73-79 (2016) - [c76]Emeshaw Ashenafi, Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Detection of biochemical molecules using CM-SOFFET based biosensor. ISCAS 2016: 2831-2834 - [c75]Abdullah G. Alharbi, Mohammed E. Fouda, Zainulabideen J. Khalifa, Masud H. Chowdhury:
Simple generic memristor emulator for voltage-controlled models. MWSCAS 2016: 1-4 - [c74]MunEm Hossain, Masud H. Chowdhury:
Innovative device source/drain and channel implantation for MOS transistors in ultra low power subthreshold circuit applications. NEWCAS 2016: 1-4 - [c73]Emeshaw Ashenafi, Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Low voltage Flash memory design based on floating gate SOFFET. SoCC 2016: 129-132 - 2015
- [j13]Nahid M. Hossain, Masud H. Chowdhury:
Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory. ACM J. Emerg. Technol. Comput. Syst. 12(1): 2:1-2:17 (2015) - [j12]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing. Microelectron. J. 46(10): 981-987 (2015) - [c72]Abdullah G. Alharbi, Zainulabideen J. Khalifa, Mohamed E. Fouda, Masud H. Chowdhury:
A new simple emulator circuit for current controlled memristor. ICECS 2015: 288-291 - [c71]Abdullah G. Alharbi, Mohamed E. Fouda, Masud H. Chowdhury:
A novel memristor emulator based only on an exponential amplifier and CCII+. ICECS 2015: 376-379 - [c70]Abdullah G. Alharbi, Zainulabideen J. Khalifa, Mohammed E. Fouda, Masud H. Chowdhury:
Memristor emulator based on single CCII. ICM 2015: 174-177 - [c69]Muhammad Sanaullah, Masud H. Chowdhury:
Multilayer molybdenum disulfide (MoS2) based tunnel transistor. ISCAS 2015: 1929-1932 - [c68]Abdul Hamid Bin Yousuf, Nahid M. Hossain, Masud H. Chowdhury:
Performance analysis of through silicon via (TSV) and through glass via (TGV) for different materials. ISCAS 2015: 1957-1960 - [c67]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Analysis of subthreshold swing in multichannel tunneling carbon nanotube field effect transistor (MT-CNTFET). ISCAS 2015: 2309-2312 - [c66]Nahid M. Hossain, Jitendra Koppu, Masud H. Chowdhury:
Analysis of radiation effect on the threshold voltage of flash memory device. ISCAS 2015: 2896-2899 - [c65]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET). ISQED 2015: 615-619 - [c64]Abdullah G. Alharbi, Mohammed E. Fouda, Masud H. Chowdhury:
Memristor emulator based on practical current controlled model. MWSCAS 2015: 1-4 - [c63]Ritesh Chowdri, Nahid M. Hossain, Masud H. Chowdhury:
High-speed graphene based quantum-optical interconnect design. MWSCAS 2015: 1-4 - [c62]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Current voltage characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). MWSCAS 2015: 1-4 - [c61]MunEm Hossain, Masud H. Chowdhury:
New three dimensional doping profile for devices in subthreshold circuit. MWSCAS 2015: 1-4 - [c60]Munem Hossain, Muhammad Sanaullah, Abdul Hamid Bin Yousuf, Azzedin Es-Saki, Masud H. Chowdhury:
Analytical analysis of the contact resistance (Rc) of metal-MoS2 interface. MWSCAS 2015: 1-4 - [c59]Muhammad Sanaullah, Masud H. Chowdhury:
Subthreshold swing characteristics of multilayer MoS2 tunnel FET. MWSCAS 2015: 1-4 - [c58]Muhammad Sanaullah, Masud H. Chowdhury:
Optimization of ON current in multilayer Molybdenum Disulfide (MoS2) based tunnel field effect transistor. MWSCAS 2015: 1-4 - [i1]Mohamed S. Hefeida, Masud H. Chowdhury:
Improved Model for Wire-Length Estimation in Stochastic Wiring Distribution. CoRR abs/1502.05931 (2015) - 2014
- [c57]Nahid M. Hossain, Masud H. Chowdhury:
Multilayer graphene nanoribbon floating gate transistor for flash memory. ISCAS 2014: 806-809 - [c56]Muhammad Sanaullah, Masud H. Chowdhury:
Analysis of RLC interconnect delay model using second order approximation. ISCAS 2014: 2756-2759 - [c55]Munem Hossain, Masud H. Chowdhury:
Transistor doping profile optimization for low power subthreshold circuits. MWSCAS 2014: 33-36 - [c54]Muhammad Sanaullah, Masud H. Chowdhury:
A new real pole delay model for RLC interconnect using second order approximation. MWSCAS 2014: 238-241 - [c53]Nahid M. Hossain, Masud H. Chowdhury:
Graphene and CNT based flash memory: Impacts of scaling control and tunnel oxide thickness. MWSCAS 2014: 985-988 - [c52]Muhammad Sanaullah, Masud H. Chowdhury:
Neural network based classification of stressed speech using nonlinear spectral and cepstral features. NEWCAS 2014: 33-36 - [c51]Nahid M. Hossain, Md Belayat Hossain, Masud H. Chowdhury:
Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operation. SoCC 2014: 24-28 - [c50]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET). SoCC 2014: 152-155 - [c49]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET). SoCC 2014: 156-159 - 2013
- [c48]Nahid M. Hossain, MunEm Hossain, Abdul Hamid Bin Yousuf, Masud H. Chowdhury:
Thermal aware Graphene based Through Silicon Via design for 3D IC. 3DIC 2013: 1-4 - [c47]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Analytical model to estimate the subthreshold swing of SOI FinFET. ICECS 2013: 52-55 - [c46]Emeshaw Ashenafi, Masud H. Chowdhury:
Active on-chip voltage regulator based on second generation current conveyor. ICECS 2013: 605-608 - [c45]Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Silicon on ferroelectric insulator field effect transistor (SOF-FET) for ultra low power design. MWSCAS 2013: 77-80 - [c44]MunEm Hossain, Masud H. Chowdhury:
Heat transfer simulations for pulsed laser annealing of silicon thin film. MWSCAS 2013: 732-735 - [c43]Emeshaw Ashenafi, Masud H. Chowdhury:
Implementation of active floating inductor based on second generation current conveyor for on chip voltage regulator. MWSCAS 2013: 768-771 - [c42]Md Nahid Hossain, Masud H. Chowdhury, Md. Jahidul Islam, Tajmeri Selina Akhter:
Analysis of the properties of ZnO nanoparticle for emerging applications in nanoscale domains. MWSCAS 2013: 928-931 - 2012
- [c41]Md. Sajjad Rahaman, Masud H. Chowdhury:
Exploiting negative quantum capacitance of carbon nanotube FETs for low power applications. ISCAS 2012: 3021-3024 - [c40]Md. Tanim Humayun, Juliana Gjanci, Masud H. Chowdhury:
On-chip voltage regulator without physical inductor. NEWCAS 2012: 105-108 - 2011
- [j11]Masud H. Chowdhury, Pervez Khaled, Juliana Gjanci:
An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC). Circuits Syst. Signal Process. 30(1): 89-105 (2011) - [j10]Jingye Xu, Masud H. Chowdhury:
Fast Waveform Estimation (FWE) for Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 846-856 (2011) - [j9]Juliana Gjanci, Masud H. Chowdhury:
A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC). IEEE Trans. Very Large Scale Integr. Syst. 19(11): 1949-1959 (2011) - [c39]Md. Sajjad Rahaman, Qing Duan, Masud H. Chowdhury:
Spatial- and temporal-reliability aware design for nano-scale VLSI circuits. ISCAS 2011: 1057-1060 - [c38]Md. Khaled Hassan, Md. Sajjad Rahaman, Masud H. Chowdhury:
Addressing crosstalk issue in on-chip carbon nanotube interconnects using negative capacitance. ISCAS 2011: 1407-1410 - [c37]Pritesh Vora, Masud H. Chowdhury:
A circuit implementation for dynamic thermal management techniques. ISCAS 2011: 1668-1671 - 2010
- [j8]Md. Sajjad Rahaman, Masud H. Chowdhury:
Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems. Microelectron. J. 41(1): 33-40 (2010) - [j7]Abinash Roy, Jingye Xu, Masud H. Chowdhury:
Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 338-342 (2010)
2000 – 2009
- 2009
- [j6]Shriram Krishnamoorthy, Masud H. Chowdhury:
Investigation and a practical compact network model of thermal stress in integrated circuits. Integr. Comput. Aided Eng. 16(2): 131-140 (2009) - [c36]Md. Sajjad Rahaman, Masud H. Chowdhury, Irfan Nasir, Lih-Tyng Hwang:
VSIB: A Sensor Bus Architecture for Smart-Sensor Network. CSIE (3) 2009: 436-439 - [c35]Md. Sajjad Rahaman, Masud H. Chowdhury:
Crosstalk Avoidance and Error-correction Coding for Coupled RLC Interconnects. ISCAS 2009: 141-144 - [e1]Mark Burgin, Masud H. Chowdhury, Chan H. Ham, Simone A. Ludwig, Weilian Su, Sumanth Yenduri:
CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31 - April 2, 2009, Los Angeles, California, USA, 7 Volumes. IEEE Computer Society 2009, ISBN 978-0-7695-3507-4 [contents] - 2008
- [j5]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Noise separation in analog integrated circuits using independent component analysis technique. Integr. Comput. Aided Eng. 15(2): 163-180 (2008) - [j4]Jingye Xu, Vivek Nigam, Abinash Roy, Masud H. Chowdhury:
Compound noise separation in digital circuits using blind source separation. Microelectron. J. 39(8): 1083-1092 (2008) - [c34]Shriram Krishnamoorthy, Masud H. Chowdhury:
Compact thermal network model: Realization and reduction. EIT 2008: 389-394 - [c33]Md. Sajjad Rahaman, Masud H. Chowdhury:
BER performance comparison between CDMA and UWB for RF/wireless interconnect application. EIT 2008: 494-497 - [c32]Md. Sajjad Rahaman, Masud H. Chowdhury:
Improved ber performance in intra-chip rf/wireless interconnect systems. ACM Great Lakes Symposium on VLSI 2008: 303-308 - [c31]Jingye Xu, Pervez Khaled, Masud H. Chowdhury:
Fast bus waveform estimation at the presence of coupling noise. ACM Great Lakes Symposium on VLSI 2008: 339-342 - [c30]Abinash Roy, Jingye Xu, Masud H. Chowdhury:
Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects. ICECS 2008: 1055-1058 - [c29]Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled:
Innovative power gating for leakage reduction. ISCAS 2008: 1568-1571 - [c28]Abinash Roy, Masud H. Chowdhury:
Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects. ISCAS 2008: 2426-2429 - [c27]Md. Sajjad Rahaman, Masud H. Chowdhury:
Time diversity approach for intra-chip RF/wireless interconnect systems. ISCAS 2008: 2434-2437 - [c26]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Optimization technique for flip-flop inserted global interconnect. ISCAS 2008: 3386-3389 - [c25]Jingye Xu, Pervez Khaled, Masud H. Chowdhury:
Full waveform accuracy to estimate delay in coupled digital circuits. ISCAS 2008: 3414-3417 - [c24]Masud H. Chowdhury, Juliana Gjanci, Pervez Khaled:
Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip. ISVLSI 2008: 437-440 - 2007
- [j3]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Power Consumption and BER of Flip-Flop Inserted Global Interconnect. VLSI Design 2007: 42829:1-42829:8 (2007) - [c23]Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury:
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. DAC 2007: 184-187 - [c22]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. DATE 2007: 1218-1223 - [c21]Jingye Xu, Masud H. Chowdhury:
Accurate Delay Estimation in the Presence of Coupling Noise using Complete Waveform Accuracy. ICECS 2007: 166-169 - [c20]Abinash Roy, Sharada Jha, Masud H. Chowdhury:
Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects. ICECS 2007: 705-708 - [c19]Md. Sajjad Rahaman, Masud H. Chowdhury:
Multi-Carrier CDMA-Interconnect for Inter- and Intra-ULSI Communications. ICECS 2007: 1059-1062 - [c18]Shriram Krishnamoorthy, Masud H. Chowdhury:
Analysis of Spatial Temperature Distribution in ICs. ICECS 2007: 1272-1275 - [c17]Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury:
Delay and Clock Skew Variation due to Coupling Capacitance and Inductance. ISCAS 2007: 621-624 - [c16]Abinash Roy, Masud H. Chowdhury:
Global Interconnect Optimization in the Presence of On-chip Inductance. ISCAS 2007: 885-888 - [c15]Jingye Xu, Abinash Roy, Masud H. Chowdhury:
Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. ISCAS 2007: 3716-3719 - 2006
- [j2]Masud H. Chowdhury, Yehea I. Ismail:
Realistic scalability of noise in dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 637-641 (2006) - [c14]Pervez Khaled, Masud H. Chowdhury:
Prospects and Challenges of Handling Power Bus Modeling and Supply Noise in Package-Chip C0-design Approach. APCCAS 2006: 1107-1111 - [c13]Abinash Roy, Masud H. Chowdhury:
Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect. APCCAS 2006: 1422-1425 - [c12]Geetanjali Kshirsagar, Masud H. Chowdhury:
Optical Interconnect Technology; Photons Based Signal Communication. APCCAS 2006: 1426-1429 - [c11]Vivek Nigam, Masud H. Chowdhury, Roland Priemer:
Separation of Individual Noise Sources from Compound Noise Measurements in Digital Circuits. APCCAS 2006: 1603-1606 - [c10]Chuen M. Tan, Masud H. Chowdhury:
Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits. APCCAS 2006: 2004-2007 - [c9]Jingye Xu, Masud H. Chowdhury:
Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining. ICECS 2006: 1061-1064 - [c8]Vivek Nigam, Masud H. Chowdhury, Roland Priemer:
Compound noise analysis in digital circuits using blind source separation. ISCAS 2006 - 2005
- [j1]Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail:
Realizable reduction of interconnect circuits including self and mutual inductances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 271-277 (2005) - [c7]Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail:
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. DSN 2005: 770-779 - 2004
- [c6]Masud H. Chowdhury, Yehea I. Ismail:
Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs]. CICC 2004: 505-508 - [c5]Masud H. Chowdhury, Yehea I. Ismail:
Possible Noise Failure Modes in Static and Dynamic Circuits. IWSOC 2004: 123-126 - 2003
- [c4]Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail:
Realizable RLCK circuit crunching. DAC 2003: 226-231 - [c3]Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter:
Realizable reduction of RLC circuits using node elimination. ISCAS (3) 2003: 494-497 - [c2]Masud H. Chowdhury, Yehea I. Ismail:
Analysis of Coupling Noise in Dynamic Circuit. IWSOC 2003: 320-325 - 2002
- [c1]Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter:
Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance. ISCAS (4) 2002: 197-200
Coauthor Index
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last updated on 2025-01-20 22:59 CET by the dblp team
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