Article

Effects of coupling capacitance and inductance on delay uncertainty and clock skew

Authors:

Abinash Roy,

Noha Mahmoud,

Masud H. ChowdhuryAuthors Info & Claims

DAC '07: Proceedings of the 44th annual Design Automation Conference

Pages 184 - 187

https://doi.org/10.1145/1278480.1278525

Published: 04 June 2007 Publication History

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Abstract

With the continuous increase of circuit density, interconnect length, and aspect ratio, the influence of capacitive and inductive coupling on timing characteristics of integrated circuits has become very critical. In this paper, the effects of capacitive and inductive coupling on delay uncertainty and clock skew have been analyzed. Analytical observations and simulation results show that coupling capacitance and mutual inductance have opposite impacts on delay and clock skew variations. It is illustrated that while capacitive coupling worsens both variations, growing inductive coupling can actually counter-balance the negative impacts to some degree.

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Sharma DKaushik BSharma R(2012)Qualitative Optimization of Coupling Parasitics and Driver Width in Global VLSI InterconnectsAdvances in Computer Science and Information Technology. Computer Science and Engineering10.1007/978-3-642-27308-7_1(1-10)Online publication date: 2012
https://doi.org/10.1007/978-3-642-27308-7_1
Roy AXu JChowdhury M(2010)Analysis of the impacts of signal slew and skew on the behavior of coupled RLC interconnects for different switching patternsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201191118:2(338-342)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2011911
Yu HHe LFrank Chang M(2009)Robust On-Chip Signaling by Staggered and Twisted BundleIEEE Design & Test10.1109/MDT.2009.12126:5(92-104)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1109/MDT.2009.121

Index Terms

Effects of coupling capacitance and inductance on delay uncertainty and clock skew
1. Hardware
  1. Hardware validation

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DAC '07: Proceedings of the 44th annual Design Automation Conference

June 2007

1016 pages

ISBN:9781595936271

DOI:10.1145/1278480

General Chair:
Steven P. Levitan
Univ. of Pittsburgh, Pittsburgh, PA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 04 June 2007

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Sharma DKaushik BSharma R(2012)Qualitative Optimization of Coupling Parasitics and Driver Width in Global VLSI InterconnectsAdvances in Computer Science and Information Technology. Computer Science and Engineering10.1007/978-3-642-27308-7_1(1-10)Online publication date: 2012
https://doi.org/10.1007/978-3-642-27308-7_1
Roy AXu JChowdhury M(2010)Analysis of the impacts of signal slew and skew on the behavior of coupled RLC interconnects for different switching patternsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201191118:2(338-342)Online publication date: 1-Feb-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2011911
Yu HHe LFrank Chang M(2009)Robust On-Chip Signaling by Staggered and Twisted BundleIEEE Design & Test10.1109/MDT.2009.12126:5(92-104)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1109/MDT.2009.121

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Skew management of NBTI impacted gated clock trees

Dual-Vth leakage reduction with fast clock skew scheduling enhancement

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew

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Skew management of NBTI impacted gated clock trees

Dual-Vth leakage reduction with fast clock skew scheduling enhancement

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew

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