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Martin Saint-Laurent
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2010 – 2019
- 2015
- [j2]Martin Saint-Laurent, Paul Bassett, Ken Lin, Baker Mohammad
, Yuhe Wang, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Marzio Pedrali-Noy, Willie Anderson:
A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications. IEEE J. Solid State Circuits 50(1): 81-91 (2015) - [c9]Vijay Kiran Kalyanam, Martin Saint-Laurent, Jacob A. Abraham:
Power-aware multi-voltage custom memory models for enhancing RTL and low power verification. ICCD 2015: 24-31 - [c8]N. N. Mojumder, Seung Chul Song, K. Rim, J. Xu, Joseph Wang, J. Zhu, Milena Vratonjic, K. Lin, Martin Saint-Laurent, Paul Bassett, Geoffrey Yeap:
Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization. VLSIC 2015: 84- - 2014
- [c7]Martin Saint-Laurent, Paul Bassett, Ken Lin, Yuhe Wang, Son Le, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Willie Anderson:
10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications. ISSCC 2014: 176-177 - 2012
- [c6]Paul Bassett, Martin Saint-Laurent:
Energy efficient design techniques for a digital signal processor. ICICDT 2012: 1-4 - 2010
- [c5]Martin Saint-Laurent, Animesh Datta:
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology. ISLPED 2010: 159-164
2000 – 2009
- 2008
- [c4]Baker Mohammad
, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham:
Cache Design for Low Power and High Yield. ISQED 2008: 103-107 - 2007
- [j1]Martin Saint-Laurent:
A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 834-844 (2007) - [c3]Martin Saint-Laurent, Baker Mohammad
, Paul Bassett:
A 65-nm pulsed latch with a single clocked transistor. ISLPED 2007: 347-350 - 2002
- [c2]Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan:
Optimal Sequencing Energy Allocation for CMOS Integrated Systems. ISQED 2002: 194-199 - 2001
- [c1]Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl:
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. ICCD 2001: 214-220
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