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A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology

Authors:

Martin Saint-Laurent,

Animesh DattaAuthors Info & Claims

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

Pages 159 - 164

https://doi.org/10.1145/1840845.1840878

Published: 18 August 2010 Publication History

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Abstract

This paper discusses a novel clock gating cell (CGC) optimized for low-power and low-voltage operation. First, the limitations of the conventional CGC topology are analyzed and several improvements are proposed. Next, the new CGC topology is introduced and compared to the conventional one in terms of dynamic clock power, leakage, area, timing, and low-voltage operation. Finally, the paper discusses the silicon measurements taken to verify the correct functionality of the new circuit in a 45-nm technology optimized for low standby power.

References

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M. Keating et al., Low Power Methodology Manual, Chapter 2, Springer, 2007.

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[2]

L. Benini and G. De Micheli, "Automatic Synthesis of Low-Power Gated-Clock Finite-State Machines", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 1996.

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[3]

R. Jotwani et al., "An x86--64 Core Implemented in 32nm SOI CMOS", IEEE International Solid-State Circuits Conference, 2010.

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L. S. Hong and A. K. Wong, "Clock Gater Standard Cell Design", IEEE Conference on Electron Devices and Solid-State Circuits, 2003.

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Cited By

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Fan XStuijt JLiu BGemmeke T(2019)Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoTIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2018.287302666:3(941-954)Online publication date: Mar-2019
https://doi.org/10.1109/TCSI.2018.2873026
Noor TSalman E(2019)A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702507(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702507
Otadoy JGenesis Jimenez KHora JCristine O. Calimpusan RLowaton A(2019)Analysis and Comparison of Novel Clock Gating Cell Topologies in 65nm CMOS Process Technology2019 IEEE 11th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management ( HNICEM )10.1109/HNICEM48295.2019.9073358(1-6)Online publication date: Nov-2019
https://doi.org/10.1109/HNICEM48295.2019.9073358
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A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology
1. Hardware
  1. Very large scale integration design

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Published In

ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

August 2010

458 pages

ISBN:9781450301466

DOI:10.1145/1840845

General Chairs:
Vojin Oklobdzija
University of Texas, Dallas
,
Barry Pangle
Mentor Graphics
,
Naehyuck Chang
Seoul National University
,
Program Chairs:
Naresh Shanbhag
University of Illinois at Urbana-Champaign
,
Chris H. Kim
University of Minnesota

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 18 August 2010

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ISLPED'10: International Symposium on Low Power Electronics and Design

August 18 - 20, 2010

Texas, Austin, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Fan XStuijt JLiu BGemmeke T(2019)Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoTIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2018.287302666:3(941-954)Online publication date: Mar-2019
https://doi.org/10.1109/TCSI.2018.2873026
Noor TSalman E(2019)A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702507(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702507
Otadoy JGenesis Jimenez KHora JCristine O. Calimpusan RLowaton A(2019)Analysis and Comparison of Novel Clock Gating Cell Topologies in 65nm CMOS Process Technology2019 IEEE 11th International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment, and Management ( HNICEM )10.1109/HNICEM48295.2019.9073358(1-6)Online publication date: Nov-2019
https://doi.org/10.1109/HNICEM48295.2019.9073358
Kim MKim AKim YKim CKim DKim JLee DLee HPyo JShin YSon J(2018)Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling2018 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2018.8351444(1-5)Online publication date: May-2018
https://doi.org/10.1109/ISCAS.2018.8351444
Saint-Laurent MBassett PLin KMohammad BWang YChen XAlradaideh MWernimont TAyyar KBui DGalbi DLester APedrali-Noy MAnderson W(2015)A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile ApplicationsIEEE Journal of Solid-State Circuits10.1109/JSSC.2014.237145450:1(81-91)Online publication date: Jan-2015
https://doi.org/10.1109/JSSC.2014.2371454
Saint-Laurent MBassett PLin KWang YLe SChen XAlradaideh MWernimont TAyyar KBui DGalbi DLester AAnderson W(2014)10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)10.1109/ISSCC.2014.6757388(176-177)Online publication date: Feb-2014
https://doi.org/10.1109/ISSCC.2014.6757388
Nejat MAbdevand MFarahani A(2013)A novel circuit topology for clock-gating-cell suitable for sub/near-threshold designsThe 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013)10.1109/CADS.2013.6714236(45-49)Online publication date: Oct-2013
https://doi.org/10.1109/CADS.2013.6714236
Durgam AChoi K(2013)Optimized clock gating cell for low power design in nanoscale CMOS technologyFifth Asia Symposium on Quality Electronic Design (ASQED 2013)10.1109/ASQED.2013.6643569(85-88)Online publication date: Aug-2013
https://doi.org/10.1109/ASQED.2013.6643569

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Low-power anti-aging zero skew clock gating

Clock routing for low power

Ultra low-power clocking scheme using energy recovery and clock gating

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