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ORCIDAthanasios Ramkaj
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2020 – today
- 2024
[j4]Moon Hyung Jang
, Maddy Hays, Wei-Han Yu, Changuk Lee, Pietro Caragiulo, Athanasios T. Ramkaj, Pingyu Wang, A. J. Phillips, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E. J. Chichilnisky, Boris Murmann, Dante G. Muratore:
A 1024-Channel 268-nW/Pixel 36×36 μm2/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces. IEEE J. Solid State Circuits 59(4): 1123-1136 (2024)- [c7]Rohan Doshi, Massimo Giordano, Justin Olah, Zhidong Cao, Moon Hyung Jang, Luke R. Upton, Athanasios Ramkaj, Boris Murmann:
Medusa: A 0.83/4.6μJ/Frame 86/91.6%-CIFAR-10 TinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS. VLSI Technology and Circuits 2024: 1-2 - 2023
- [b1]Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier:
Multi-Gigahertz Nyquist Analog-to-Digital Converters - Architecture and Circuit Innovations in Deep-Scaled CMOS and FinFET Technologies, 3. Springer 2023, ISBN 978-3-031-22708-0, pp. 1-256 - [c6]Athanasios Ramkaj, Michael Perrott, Baher Haroun, Boris Murmann:
High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design. ISCAS 2023: 1-5 - 2022
- [j3]Athanasios T. Ramkaj, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Filip Tavernier:
A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4404-4414 (2022) - [c5]Pietro Caragiulo, Athanasios Ramkaj, Amin Arbabian, Boris Murmann:
A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS. ESSCIRC 2022: 329-332 - [c4]Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier:
A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET. VLSI Technology and Circuits 2022: 100-101 - 2020
- [j2]Athanasios T. Ramkaj, Juan Carlos Pena Ramos, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Marian Verhelst, Filip Tavernier:
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS. IEEE J. Solid State Circuits 55(6): 1553-1564 (2020)
2010 – 2019
- 2019
- [c3]Athanasios T. Ramkaj, Michiel S. J. Steyaert, Filip Tavernier:
A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS. ESSCIRC 2019: 167-170 - [c2]Athanasios Ramkaj, Juan Carlos Pena Ramos, Yifan Lyu, Maarten Strackx, Marcel J. M. Pelgrom, Michiel Steyaert, Marian Verhelst, Filip Tavernier:
A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS. ISSCC 2019: 62-64 - 2018
- [j1]Athanasios Ramkaj, Maarten Strackx, Michiel S. J. Steyaert, Filip Tavernier:
A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS. IEEE J. Solid State Circuits 53(7): 1889-1901 (2018) - 2017
- [c1]Athanasios Ramkaj, Maarten Strackx, Michiel Steyaert, Filip Tavernier:
A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS. ESSCIRC 2017: 167-170
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