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2020 – today
- 2024
[j12]Kyeongho Lee
, Joonhyung Kim, Jongsun Park:
A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations. IEEE J. Solid State Circuits 59(6): 1926-1937 (2024)- 2023
- [j11]Sungsoo Cheon, Kyeongho Lee, Jongsun Park:
A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2085-2097 (2023) - [j10]Junhyun Song, Kyeongho Lee, Jongsun Park:
Low Area and Low Power Threshold Implementation Design Technique for AES S-Box. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 1169-1173 (2023) - 2022
- [c13]Hyunchul Park, Kyeongho Lee, Jongsun Park:
A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. AICAS 2022: 455-458 - [c12]Kyeongho Lee, Joonhyung Kim, Jongsun Park:
Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion. ICCAD 2022: 143:1-143:8 - [c11]Joonhyung Kim, Kyeongho Lee, Jongsun Park:
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. ISLPED 2022: 6:1-6:6 - [i2]Joonhyung Kim, Kyeongho Lee, Jongsun Park:
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. CoRR abs/2211.16008 (2022) - 2021
- [j9]Kyeongho Lee, Woong Choi, Jongsun Park:
A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge. IEEE J. Solid State Circuits 56(8): 2574-2584 (2021) - [c10]Kyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park:
A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. DAC 2021: 739-744 - 2020
- [c9]Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park:
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. DAC 2020: 1-6 - [i1]Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park:
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. CoRR abs/2008.03378 (2020)
2010 – 2019
- 2019
- [c8]Kyeongho Lee, Geon Ko, Jongsun Park:
Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme. ISCAS 2019: 1-4 - 2018
- [c7]Woong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park:
Content addressable memory based binarized neural network accelerator using time-domain signal processing. DAC 2018: 138:1-138:6 - [c6]Woong Choi, Kyeongho Lee, Jongsun Park:
Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme. ISCAS 2018: 1-4 - 2015
- [c5]Suh-Yeon Dong, Bo-Kyeong Kim, Kyeongho Lee, Soo-Young Lee:
A Preliminary Study on Human Trust Measurements by EEG for Human-Machine Interactions. HAI 2015: 265-268 - [c4]Dong-Gun Lee, Kyeongho Lee, Soo-Young Lee:
Implicit Shopping Intention Recognition with Eye Tracking Data and Response Time. HAI 2015: 295-298
2000 – 2009
- 2008
- [c3]Taesang Choi, Sangsik Yoon, Dongwon Kang, Sangwan Kim, Joonkyung Lee, Kyeongho Lee:
Wire-speed application flow generation in hardware platform for multi-gigabit traffic monitoring. NOMS 2008: 184-191 - 2006
- [c2]Taesang Choi, Sangsik Yoon, Dongwon Kang, Sangwan Kim, Joonkyung Lee, Kyeongho Lee:
Novel Traffic Measurement Methodology for High Precision Applications Awareness in Multi-gigabit Networks. APNOMS 2006: 63-72 - 2005
- [j8]Hyungki Huh, Yido Koo, Kang-Yoon Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer. IEEE J. Solid State Circuits 40(11): 2228-2236 (2005) - 2003
- [j7]Kang-Yoon Lee, Seung-Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver. IEEE J. Solid State Circuits 38(1): 43-53 (2003) - 2002
- [j6]Yido Koo, Hyungki Huh, Yongsik Cho, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, Deog-Kyoon Jeong, Wonchan Kim:
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems. IEEE J. Solid State Circuits 37(5): 536-542 (2002) - 2001
- [j5]Kyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung-Wook Lee, Hyung Ki Huh, Deog-Kyoon Jeong, Wonchan Kim:
A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique. IEEE J. Solid State Circuits 36(5): 800-809 (2001) - 2000
- [j4]Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance. IEEE J. Solid State Circuits 35(3): 377-384 (2000)
1990 – 1999
- 1999
- [c1]Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim:
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells. CICC 1999: 299-302 - 1998
- [j3]Kyeongho Lee, Yeshik Shin, Sungjoon Kim, Deog-Kyoon Jeong, Gyudong Kim, Bruce Kim, Victor Da Costa:
1.04 GBd low EMI digital video interface system using small swing serial link technique. IEEE J. Solid State Circuits 33(5): 816-823 (1998) - 1997
- [j2]Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim:
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL. IEEE J. Solid State Circuits 32(5): 691-700 (1997) - 1995
- [j1]Kyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog-Kyoon Jeong:
A CMOS serial link for fully duplexed data communication. IEEE J. Solid State Circuits 30(4): 353-364 (1995)
Coauthor Index
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