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2000 – 2009
- 2006
[c1]Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim:
A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control. ISSCC 2006: 233-242- 2004
- [j6]Yongsam Moon, Young-Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog-Kyoon Jeong:
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. IEEE J. Solid State Circuits 39(5): 795-803 (2004) - 2002
- [j5]Sang-Hyun Lee, Moon-Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog-Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn:
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit. IEEE J. Solid State Circuits 37(12): 1822-1830 (2002) - 2001
- [j4]Yongsam Moon, Deog-Kyoon Jeong, Gijung Ahn:
A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery. IEEE J. Solid State Circuits 36(12): 1974-1983 (2001) - 2000
- [j3]Gijung Ahn, Deog-Kyoon Jeong, Gyudong Kim:
A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission. IEEE J. Solid State Circuits 35(6): 915-918 (2000)
1990 – 1999
- 1995
- [j2]Kyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog-Kyoon Jeong:
A CMOS serial link for fully duplexed data communication. IEEE J. Solid State Circuits 30(4): 353-364 (1995) - 1994
- [j1]Wonchan Kim, Joongsik Kih, Gyudong Kim, Sanghun Jung, Gijung Ahn:
An experimental high-density DRAM cell with a built-in gain stage. IEEE J. Solid State Circuits 29(8): 978-981 (1994)
Coauthor Index
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