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2020 – today
- 2023
[c82]Shan-Hui Chou, Ting-Yun Hsiao, Jing-Yang Jou, Juinn-Dar Huang
:
An Evaluation and Architecture Exploration Engine for CNN Accelerators through Extensive Dataflow Analysis. VLSI-SoC 2023: 1-6- 2022
- [c81]Yu-Guang Chen, Tsung-Han Hsieh, Yi-Chen Ho, Jing-Yang Jou:
A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design. AICAS 2022: 250-253 - 2021
- [c80]Li-Cheng Zheng, Hao-Ju Chang, Yung-Chih Chen, Jing-Yang Jou:
1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method. ASP-DAC 2021: 469-474 - [c79]Hao-Yu Chi, Han-Chung Chang, Chih-Hsin Yang, Chien-Nan Liu, Jing-Yang Jou:
Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design. DATE 2021: 1218-1223 - [c78]Yu-Guang Chen, Hung-Yi Chiang, Chi-Wei Hsu, Tsung-Han Hsieh, Jing-Yang Jou:
A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. ISOCC 2021: 290-291 - [c77]Yu-Guang Chen, Chi-Wei Hsu, Hung-Yi Chiang, Tsung-Han Hsieh, Jing-Yang Jou:
A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks. SoCC 2021: 278-283
2010 – 2019
- 2016
- [c76]Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang, Jing-Yang Jou:
Chain-based pin count minimization for general-purpose digital microfluidic biochips. ASP-DAC 2016: 599-604 - [c75]An-Che Cheng, Iris Hui-Ru Jiang, Jing-Yang Jou:
Resource-aware functional ECO patch generation. DATE 2016: 1036-1041 - [c74]Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He:
Wave digital filter based analog circuit emulation on FPGA. ISCAS 2016: 1286-1289 - 2015
- [j44]Gung-Yu Pan, Chih-Yen Lai, Jing-Yang Jou, Bo-Cheng Charles Lai:
Power-Efficient Instancy Aware DRAM Scheduling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(4): 942-953 (2015) - [j43]Bo-Cheng Charles Lai, Hsien-Kai Kuo, Jing-Yang Jou:
A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs. IEEE Trans. Computers 64(4): 884-898 (2015) - [j42]Gung-Yu Pan, Jed Yang, Jing-Yang Jou, Bo-Cheng Charles Lai:
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors. ACM Trans. Embed. Comput. Syst. 14(4): 70:1-70:24 (2015) - 2014
- [j41]Bu-Ching Lin, Juinn-Dar Huang, Jing-Yang Jou:
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(4): 931-939 (2014) - [j40]Bu-Ching Lin, Ming-En Shih, Juinn-Dar Huang, Jing-Yang Jou:
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors. J. Inf. Sci. Eng. 30(4): 991-1014 (2014) - [j39]Gung-Yu Pan, Jing-Yang Jou, Bo-Cheng Lai:
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors. ACM Trans. Design Autom. Electr. Syst. 19(4): 33:1-33:23 (2014) - [j38]An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou:
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. ACM Trans. Design Autom. Electr. Syst. 20(1): 7:1-7:23 (2014) - [j37]Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou:
Reducing Contention in Shared Last-Level Cache for Throughput Processors. ACM Trans. Design Autom. Electr. Syst. 20(1): 12:1-12:28 (2014) - [c73]Chih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo, Jing-Yang Jou:
A read-write aware DRAM scheduling for power reduction in multi-core systems. ASP-DAC 2014: 604-609 - [c72]Gung-Yu Pan, Bo-Cheng Charles Lai, Sheng-Yen Chen, Jing-Yang Jou:
A learning-on-cloud power management policy for smart devices. ICCAD 2014: 376-381 - 2013
- [c71]Hsien-Kai Kuo, Ta-Kan Yen, Bo-Cheng Charles Lai, Jing-Yang Jou:
Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs. ASP-DAC 2013: 338-343 - 2012
- [j36]Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou:
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(2): 559-566 (2012) - [c70]Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Charles Lai, Jing-Yang Jou:
Thread affinity mapping for irregular data access on shared Cache GPGPU. ASP-DAC 2012: 659-664 - [c69]An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou:
A formal method to improve SystemVerilog functional coverage. HLDVT 2012: 56-63 - 2011
- [c68]Chi-Hui Lee, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Equivalence checking of scheduling with speculative code transformations in high-level synthesis. ASP-DAC 2011: 497-502 - [c67]Meng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou:
Mixed non-rectangular block packing for non-Manhattan layout architectures. ISQED 2011: 257-262 - [c66]Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen:
Design-for-debug layout adjustment for FIB probing and circuit editing. ITC 2011: 1-9 - 2010
- [j35]Che-Hua Shih, Ya-Ching Yang, Chia-Chih Yen, Juinn-Dar Huang, Jing-Yang Jou:
FSM-Based Formal Compliance Verification of Interface Protocols. J. Inf. Sci. Eng. 26(5): 1601-1617 (2010) - [c65]Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou:
Unleash the parallelism of 3DIC partitioning on GPGPU. SoCC 2010: 127-132 - [c64]Bu-Ching Lin, Yu-Hsiang Wang, Juinn-Dar Huang, Jing-Yang Jou:
Expandable MDC-based FFT architecture and its generator for high-performance applications. SoCC 2010: 188-192
2000 – 2009
- 2009
- [j34]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 272-284 (2009) - [j33]Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou:
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. ACM Trans. Design Autom. Electr. Syst. 15(1): 3:1-3:17 (2009) - [j32]Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 723-727 (2009) - [c63]Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu:
Multiple-Fault Diagnosis Using Faulty-Region Identification. VTS 2009: 123-128 - 2008
- [j31]Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou:
Verification of Pin-Accurate Port Connections. IEEE Des. Test Comput. 25(5): 478-486 (2008) - [c62]Kuang-Chin Cheng, Jing-Yang Jou:
Crosstalk-avoidance coding for low-power on-chip bus. ICECS 2008: 1051-1054 - 2007
- [j30]Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou:
A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23(1): 71-90 (2007) - [j29]Cheng-Yeh Wang, Chih-Bin Kuo, Jing-Yang Jou:
Hybrid Wordlength Optimization Methods of Pipelined FFT Processors. IEEE Trans. Computers 56(8): 1105-1118 (2007) - [j28]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1509-1521 (2007) - [c61]Bu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou:
A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses. ASP-DAC 2007: 165-170 - 2006
- [j27]Chia-Chih Yen, Jing-Yang Jou:
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging. IEEE Trans. Computers 55(11): 1356-1366 (2006) - [j26]Shang-Wei Tu, Yao-Wen Chang, Jing-Yang Jou:
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2258-2264 (2006) - [j25]Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou:
Reliable crosstalk-driven interconnect optimization. ACM Trans. Design Autom. Electr. Syst. 11(1): 88-103 (2006) - [c60]Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
FSM-based transaction-level functional coverage for interface compliance verification. ASP-DAC 2006: 448-453 - [c59]Chien-Hua Chen, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou:
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication. ASP-DAC 2006: 600-605 - [c58]Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou:
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. SoCC 2006: 137-140 - 2005
- [j24]Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou:
An efficient heterogeneous tree multiplexer synthesis technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1622-1629 (2005) - [c57]Liang-Yu Lin, Cheng-Yeh Wang, Pao-Jui Huang, Chih-Chieh Chou, Jing-Yang Jou:
Communication-driven task binding for multiprocessor with latency insensitive network-on-chip. ASP-DAC 2005: 39-44 - [c56]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC 2005: 323-326 - [c55]Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou:
Stimulus generation for interface protocol verification using the nondeterministic extended finite state machine model. HLDVT 2005: 87-93 - [c54]Chia-Chih Yen, Jing-Yang Jou:
An optimum algorithm for compacting error traces for efficient functional debugging. HLDVT 2005: 177-183 - [c53]Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang:
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. ISCAS (4) 2005: 4134-4137 - [c52]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. ISCAS (6) 2005: 5682-5685 - 2004
- [j23]Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen:
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Des. Test Comput. 21(2): 111-120 (2004) - [j22]Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 694-703 (2004) - [c51]Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang:
Layout techniques for on-chip interconnect inductance reduction. ASP-DAC 2004: 269-273 - [c50]Hsu-Wei Huang, Cheng-Yeh Wang, Jing-Yang Jou:
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming. ASP-DAC 2004: 280-283 - [c49]Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou:
On compliance test of on-chip bus for SOC. ASP-DAC 2004: 328-333 - [c48]Chia-Chih Yen, Jing-Yang Jou:
Enhancing sequential depth computation with a branch-and-bound algorithm. HLDVT 2004: 3-8 - [c47]Chen-Ling Chou, Chun-Yao Wang, Geeng-Wei Lee, Jing-Yang Jou:
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs. ICCD 2004: 417-419 - [c46]Yi-Wei Lin, Jing-Yang Jou:
An efficient approach for hierarchical submodule extraction. ISCAS (5) 2004: 237-240 - [c45]Lily Huang, Tai-Ying Jiang, Jing-Yang Jou, Heng-Liang Huang:
An efficient logic extraction algorithm using partitioning and circuit encoding. ISCAS (5) 2004: 249-252 - [c44]Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang:
RLC effects on worst-case switching pattern for on-chip buses. ISCAS (2) 2004: 945-948 - [c43]Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang:
Verification on Port Connections. ITC 2004: 830-836 - 2003
- [j21]Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou:
A Design-for-Verification Technique for Functional Pattern Reduction. IEEE Des. Test Comput. 20(2): 48-55 (2003) - [j20]Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An Efficient Power Model for IP-Level Complex Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(8): 2073-2080 (2003) - [j19]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 104-114 (2003) - [c42]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An automatic interconnection rectification technique for SoC design integration. ASP-DAC 2003: 108-111 - [c41]Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floorplanning and buffer block planning. ASP-DAC 2003: 431-434 - [c40]Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An efficient IP-level power model for complex digital circuits. ASP-DAC 2003: 610-613 - [c39]Che-Hua Shih, Jing-Yang Jou:
An efficient approach for error diagnosis in HDL design. ISCAS (4) 2003: 732-735 - [c38]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
SoC design integration by using automatic interconnection rectification. ISCAS (4) 2003: 744-747 - 2002
- [j18]Heng-Liang Huang, Jing-Yang Jou:
Bootstrap Monte Carlo with Adaptive Stratification for Power Estimation. J. Circuits Syst. Comput. 11(4): 333-350 (2002) - [j17]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 466-479 (2002) - [j16]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1225-1232 (2002) - [c37]Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou:
Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium 2002: 362-367 - [c36]Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou:
A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS 2002: 149-154 - 2001
- [j15]Yi-Jong Yeh, Sy-Yen Kuo, Jing-Yang Jou:
Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 172-176 (2001) - [j14]Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Unified functional decomposition via encoding for FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 251-260 (2001) - [c35]Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou:
An efficient design-for-verification technique for HDLs. ASP-DAC 2001: 103-108 - [c34]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. Asian Test Symposium 2001: 431-436 - [c33]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. HLDVT 2001: 145-150 - [c32]Li-An Sung, Iris Hui-Ru Jiang, Yoh-Wen Chang, Jing-Yang Jou, Jiin-Chuan Wu, Tai-Sheng Feng:
On placement and routing of wafer scale memory. ICECS 2001: 883-887 - [c31]Hen-Ming Lin, Jing-Yang Jou:
On tri-state buffer inference in HDL synthesis. ISCAS (5) 2001: 45-48 - [c30]Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An AVPG for SOC design verification with port order fault model. ISCAS (5) 2001: 259-262 - [c29]Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen:
Grouped input power sensitive transition an input sequence compaction technique for power estimation. ISCAS (5) 2001: 471-474 - [c28]Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou:
Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED 2001: 372-377 - 2000
- [j13]Chien-Nan Jimmy Liu, Jing-Yang Jou:
An Automatic Controller Extractor for HDL Descriptions at the RTL. IEEE Des. Test Comput. 17(3): 72-77 (2000) - [j12]Hen-Ming Lin, Jing-Yang Jou:
On computing the minimum feedback vertex set of a directed graph bycontraction operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 295-307 (2000) - [j11]Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou:
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 999-1010 (2000) - [j10]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 392-400 (2000) - [c27]Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A new method for constructing IP level power model based on power sensitivity. ASP-DAC 2000: 135-140 - [c26]Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu:
Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17 - [c25]Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou, Ming-Chih Lai, Hsing-Ming Juan:
A novel approach for functional coverage measurement in HDL. ISCAS 2000: 217-220 - [c24]Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou:
Optimal reliable crosstalk-driven interconnect optimization. ISPD 2000: 128-133
1990 – 1999
- 1999
- [j9]Jyh-Mou Tseng, Jing-Yang Jou:
Two-level logic minimization for low power. ACM Trans. Design Autom. Electr. Syst. 4(1): 52-69 (1999) - [j8]Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A structure-oriented power modeling technique for macrocells. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 380-391 (1999) - [c23]Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang:
Hierarchical Floorplan Design on the Internet. ASP-DAC 1999: 189-192 - [c22]Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang:
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. DAC 1999: 90-95 - [c21]Chien-Nan Jimmy Liu, Jing-Yang Jou:
An Efficient Functional Coverage Test for HDL Descriptions at RTL. ICCD 1999: 325-327 - [c20]Hen-Ming Lin, Jing-Yang Jou:
Computing Minimum Feedback Vertex Sets by Contraction Operations and its Applications on CAD. ICCD 1999: 364- - 1998
- [j7]Shing-Wu Tung, Jing-Yang Jou:
A Logical Fault Model for Library Coherence Checking. J. Inf. Sci. Eng. 14(3): 567-586 (1998) - [j6]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang:
On circuit clustering for area/delay tradeoff under capacity and pin constraints. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 634-642 (1998) - [c19]Shing-Wu Tung, Jing-Yang Jou:
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. Asian Test Symposium 1998: 402-407 - [c18]Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang:
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. DAC 1998: 712-717 - 1997
- [j5]Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo:
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1015-1024 (1997) - [c17]Jyh-Mou Tseng, Jing-Yang Jou:
A power driven two-level logic optimizer. ASP-DAC 1997: 113-116 - [c16]Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei:
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. ASP-DAC 1997: 259-264 - [c15]Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A power modeling and characterization method for macrocells using structure information. ICCAD 1997: 502-506 - [c14]Jing-Yang Jou, Ming-Chang Nien:
Power Driven Partial Scan. ICCD 1997: 642-647 - 1996
- [c13]Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao:
Easily Testable Data Path Allocation Using Input/Output Registers. Asian Test Symposium 1996: 142- - [c12]Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo:
An Efficient PRPG Strategy By Utilizing Essential Faults. Asian Test Symposium 1996: 199-204 - [c11]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping. ICCAD 1996: 13-17 - [c10]Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
A power modeling and characterization method for the CMOS standard cell library. ICCAD 1996: 400-404 - 1995
- [j4]Jing-Yang Jou, Kwang-Ting (Tim) Cheng:
Timing-Driven Partial Scan. IEEE Des. Test Comput. 12(4): 52-59 (1995) - [c9]Jing-Yang Jou:
An effective BIST design for PLA. Asian Test Symposium 1995: 286-292 - [c8]Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen:
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture. ICCAD 1995: 359-363 - 1992
- [j3]Kwang-Ting Cheng, Jing-Yang Jou:
A functional fault model for sequential machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9): 1065-1073 (1992) - 1991
- [c7]Jing-Yang Jou, Kwang-Ting Cheng:
Timing-Driven Partial Scan. ICCAD 1991: 404-407 - 1990
- [c6]Kwang-Ting Cheng, Jing-Yang Jou:
A Single-State-Transition Fault Model for Sequential Machines. ICCAD 1990: 226-229 - [c5]Kwang-Ting Cheng, Jing-Yang Jou:
Functional test generation for finite state machines. ITC 1990: 162-168
1980 – 1989
- 1989
- [c4]Chin-Long Wey, Sin-Min Chang, Jing-Yang Jou:
OPAM: an efficient output phase assignment for multilevel logic minimization. ICCD 1989: 270-273 - 1988
- [j2]Jing-Yang Jou, Jacob A. Abraham:
Fault-Tolerant FFT Networks. IEEE Trans. Computers 37(5): 548-561 (1988) - [c3]Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou:
BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. DAC 1988: 409-414 - [c2]Jing-Yang Jou:
A testable PLA design with low overhead and ease of test generation. ICCD 1988: 450-453 - [c1]Jing-Yang Jou, Jacob A. Abraham:
Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. ICPP (1) 1988: 359-362 - 1986
- [j1]Jing-Yang Jou, Jacob A. Abraham:
Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures. Proc. IEEE 74(5): 732-741 (1986)
Coauthor Index
Chien-Nan Jimmy Liu
aka: Chien-Nan Liu
aka: Chien-Nan Liu
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last updated on 2024-08-03 20:09 CEST by the dblp team
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