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2020 – today
- 2024
[j6]Po-Shao Chen
, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang:
A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring. IEEE J. Solid State Circuits 59(6): 1899-1911 (2024)- 2023
- [j5]Chung-Hsuan Yang, Yi-Chung Wu, Yen-Lung Chen, Chao-Hsi Lee, Jui-Hung Hung, Chia-Hsiang Yang:
An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping. IEEE Trans. Biomed. Circuits Syst. 17(6): 1331-1341 (2023) - [c14]Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang:
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. ISSCC 2023: 44-45 - 2021
- [j4]Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang:
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. IEEE J. Solid State Circuits 56(1): 123-135 (2021) - [j3]Yen-Lung Chen, Bo-Yi Chang, Chia-Hsiang Yang, Tzi-Dar Chiueh:
A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome. IEEE Trans. Parallel Distributed Syst. 32(6): 1465-1478 (2021) - [c13]Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang:
A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring. A-SSCC 2021: 1-3 - 2020
- [c12]Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang:
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. ISSCC 2020: 322-324
2010 – 2019
- 2016
- [c11]Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He:
Wave digital filter based analog circuit emulation on FPGA. ISCAS 2016: 1286-1289 - 2015
- [c10]Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He:
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. ASP-DAC 2015: 556-561 - [c9]Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He:
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). FPGA 2015: 276 - [c8]Hsin-Ju Chang, Yen-Lung Chen, Conan Yeh, Chien-Nan Jimmy Liu:
Layout-aware analog synthesis environment with yield consideration. ISQED 2015: 589-593 - 2014
- [j2]Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li:
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 24-35 (2014) - [c7]Wei Wu, Wenyao Xu, Rahul Krishnan, Yen-Lung Chen, Lei He:
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage. DAC 2014: 82:1-82:6 - [c6]Yung-Yue Chen, Yen-Lung Chen, Bo-Hui Zhou:
Robust guidance law design for UAVs. ICCA 2014: 44-49 - [c5]Yen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, Chien-Nan Jimmy Liu:
Simultaneous optimization for low dropout regulator and its error amplifier with process variation. VLSI-DAT 2014: 1-4 - 2013
- [c4]Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, Chien-Nan Jimmy Liu:
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects. DATE 2013: 1458-1461 - [c3]Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen:
LASER: layout-aware analog synthesis environment on laker. ACM Great Lakes Symposium on VLSI 2013: 107-112 - [c2]Yen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, Chien-Nan Jimmy Liu:
A layout-aware automatic sizing approach for retargeting analog integrated circuits. VLSI-DAT 2013: 1-4 - 2012
- [j1]Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai:
A fast heuristic approach for parametric yield enhancement of analog designs. ACM Trans. Design Autom. Electr. Syst. 17(3): 35:1-35:20 (2012) - 2010
- [c1]Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu:
Behavior-level yield enhancement approach for large-scaled analog circuits. DAC 2010: 903-908
Coauthor Index
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