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2020 – today
- 2024
[j59]Yuhao Shu
, Hongtu Zhang, Qi Deng, Hao Sun, Zhaodong Lv, Yifei Li, Yajun Ha:
eCIMC: A603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations. IEEE J. Solid State Circuits 59(11): 3827-3839 (2024)- [j58]Meng Zhang, Zheng Zhang, Yifan Niu, Jiayi Li, Zewei Chen, Guoqing Li, Yajun Ha, Tinghuan Chen:
Fast Constraints Tuning via Transfer Learning and Multiobjective Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2705-2718 (2024) - [j57]Xiaoxuan Peng, Xiaohu Ge, Yajun Ha:
Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 348-358 (2024) - [c91]Yifei Li, Yuxin Zhou, Yuhao Shu, Hongyu Chen, Yajun Ha:
The Optimization of Aging-aware 8T SRAM for FPGA Configuration Memory. ISCAS 2024: 1-5 - [c90]Zhaodong Lv, Hao Sun, Yuhao Shu, Yajun Ha:
EarFDA: A Lightweight and Energy-Efficient Fall Detection Accelerator for Ear-Worn Devices. ISCAS 2024: 1-5 - [c89]Yi Wang, Yuanjin Zheng, Yajun Ha:
Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway. ISCAS 2024: 1-5 - [i5]Yi Wang, Yuanjin Zheng, Yajun Ha:
Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway. CoRR abs/2406.16369 (2024) - 2023
- [j56]Weixiong Jiang, Heng Yu, Yajun Ha:
A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1532-1545 (2023) - [j55]Weixiong Jiang, Heng Yu, Fupeng Chen, Yajun Ha:
AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2952-2965 (2023) - [j54]Rui Li, Heng Yu, Lin Li, Yajun Ha:
Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3881-3894 (2023) - [j53]Lin Li, Rui Li, Yajun Ha:
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3972-3984 (2023) - [j52]Hao Sun, Qi Deng, Xinzhe Liu, Yuhao Shu, Yajun Ha:
An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 253-265 (2023) - [j51]Hongtu Zhang, Yuhao Shu, Qi Deng, Hao Sun, Wenfeng Zhao, Yajun Ha:
WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads. IEEE Trans. Circuits Syst. I Regul. Pap. 70(10): 3964-3977 (2023) - [j50]Jianwen Luo, Xinzhe Liu, Fupeng Chen, Yajun Ha:
HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4295-4308 (2023) - [j49]Yajun Ha:
Outgoing Editorial. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4298 (2023) - [j48]Yuqi Wang, Shen Zhang, Yifei Li, Jian Chen, Wenfeng Zhao, Yajun Ha:
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation. IEEE Trans. Very Large Scale Integr. Syst. 31(5): 684-695 (2023) - [c88]Yifei Li, Jian Chen, Yuqi Wang, Zihan Yin, Hongyu Chen, Yajun Ha:
A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path. CICC 2023: 1-2 - [c87]Yuhao Shu, Hongtu Zhang, Qi Deng, Hao Sun, Yajun Ha:
CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing. CICC 2023: 1-2 - [c86]Guangyao Yan, Xinzhe Liu, Hui Wang, Yajun Ha:
Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture. DAC 2023: 1-6 - [c85]Yunhao Hu, Hao Sun, Chunxu Guo, Qi Deng, Yajun Ha:
An Energy-efficient and Fast KNN Search Accelerator for Large Scale Point Cloud Map. ICECS 2023: 1-4 - [c84]Xinzhe Liu, Jianwen Luo, David Blinder, Fupeng Chen, Heng Yu, Peter Schelkens, Francky Catthoor, Yajun Ha:
Data Partition Optimization for High Energy Efficiency by Decoupling Local Dependence in Holographic Video Decoder. ICECS 2023: 1-4 - [c83]Qixing Zhang, Hao Sun, Qi Deng, Heng Yu, Yajun Ha:
NORB: A Stream-Based and Non-Blocking FPGA Accelerator for ORB Feature Extraction. ICECS 2023: 1-4 - [c82]Yuhao Shu, Hongtu Zhang, Hao Sun, Qi Deng, Yajun Ha:
CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing. ISCAS 2023: 1-5 - [c81]Jianzhong Xiao, Hao Sun, Qi Deng, Xinzhe Liu, Hongtu Zhang, Chengzhang He, Yuhao Shu, Yajun Ha:
RPS-KNN: An Ultra-Fast FPGA Accelerator of Range-Projection-Structure K-Nearest-Neighbor Search for LiDAR Odometry in Smart Vehicles. ISCAS 2023: 1-5 - [i4]Yuhao Shu, Hongtu Zhang, Hao Sun, Mengru Zhang, Wenfeng Zhao, Qi Deng, Zhidong Tang, Yumeng Yuan, Yongqi Hu, Yu Gu, Xufeng Kou, Yajun Ha:
Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications. CoRR abs/2311.11572 (2023) - 2022
- [j47]Fupeng Chen, Heng Yu, Weixiong Jiang, Yajun Ha:
Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4873-4886 (2022) - [j46]Zhengpeng Liao, Deyang Jiang, Xiaochun Liu, Andreas Velten, Yajun Ha, Xin Lou:
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 721-734 (2022) - [j45]Guangyao Yan, Xinzhe Liu, Fupeng Chen, Hui Wang, Yajun Ha:
Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1532-1545 (2022) - [j44]Yajun Ha:
Incoming Editorial. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 2-4 (2022) - [j43]Weixiong Jiang, Heng Yu, Hongtu Zhang, Yuhao Shu, Rui Li, Jian Chen, Yajun Ha:
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA. IEEE Trans. Very Large Scale Integr. Syst. 30(4): 502-514 (2022) - [j42]Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha:
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. IEEE Trans. Very Large Scale Integr. Syst. 30(6): 769-780 (2022) - [c80]Jianwen Luo, Xinzhe Liu, Fupeng Chen, Yajun Ha:
Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs. APCCAS 2022: 476-480 - [c79]Yunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Miao Hu, Wenfeng Zhao:
WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization. ICCAD 2022: 142:1-142:9 - [c78]Chunxu Guo, Yi Wang, Fupeng Chen, Yajun Ha:
Unified Lightweight Authenticated Encryption for Resource-Constrained Electronic Control Unit. ICECS 2022 2022: 1-4 - [c77]Shaoyi Chen, Zhiqi Zhou, Yajun Ha:
An Ultra Energy Efficient Streaming-based FPGA Accelerator for Lightweight Neural Network. ISCAS 2022: 3111-3114 - 2021
- [j41]Zhenpeng He, Hao Sun, Jiawei Hou, Yajun Ha, Sören Schwertfeger:
Hierarchical topometric representation of 3D robotic maps. Auton. Robots 45(5): 755-771 (2021) - [j40]Heng Yu, Yajun Ha, Bharadwaj Veeravalli, Fupeng Chen, Hesham El-Sayed:
DVFS-Based Quality Maximization for Adaptive Applications With Diminishing Return. IEEE Trans. Computers 70(5): 803-816 (2021) - [j39]Jian Chen, Wenfeng Zhao, Yuqi Wang, Yajun Ha:
Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1520-1531 (2021) - [j38]Yajun Ha, Edoardo Bonizzoni:
Guest Editorial Special Issue on the 2021 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1565 (2021) - [j37]Hongtu Zhang, Yuhao Shu, Weixiong Jiang, Zihan Yin, Wenfeng Zhao, Yajun Ha:
A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1695-1699 (2021) - [j36]Yajun Ha, Edoardo Bonizzoni:
Guest Editorial Special Issue on the 2021 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3037 (2021) - [j35]Qi Deng, Hao Sun, Fupeng Chen, Yuhao Shu, Hui Wang, Yajun Ha:
An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3167-3171 (2021) - [j34]Jian Chen, Wenfeng Zhao, Yuqi Wang, Yajun Ha:
Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access. IEEE Trans. Circuits Syst. II Express Briefs 68(12): 3503-3507 (2021) - [c76]Xinzhe Liu, Fupeng Chen, Raees Kizhakkumkara Muhamad, David Blinder, Dessislava Nikolova, Peter Schelkens, Francky Catthoor, Yajun Ha:
Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation. DAC 2021: 613-618 - [c75]Weixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha:
TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer. DAC 2021: 1027-1032 - [c74]Yi Wang, Marc Stöttinger, Yajun Ha:
A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness. ISCAS 2021: 1-5 - [c73]Fupeng Chen, Xinzhe Liu, Heng Yu, Yajun Ha:
CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation. ISCAS 2021: 1-5 - [i3]Zhenpeng He, Hao Sun, Jiawei Hou, Yajun Ha, Sören Schwertfeger:
Hierarchical Topometric Representation of 3D Robotic Maps. CoRR abs/2111.08283 (2021) - 2020
- [j33]Huaqing Sun, Yuanyong Luo, Yajun Ha, Yinghuan Shi, Yang Gao, Qinghong Shen, Hongbing Pan:
A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 177-188 (2020) - [j32]Yajun Ha, Edoardo Bonizzoni:
Guest Editorial Special Issue on the 2020 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 805 (2020) - [j31]Yajun Ha, Edoardo Bonizzoni:
Guest Editorial Special Issue on the 2020 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1493 (2020) - [j30]Hao Sun, Xinzhe Liu, Qi Deng, Weixiong Jiang, Shaobo Luo, Yajun Ha:
Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1644-1648 (2020) - [j29]Fupeng Chen, Heng Yu, Yajun Ha:
Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles. ACM Trans. Embed. Comput. Syst. 19(2): 10:1-10:24 (2020) - [j28]Hongxi Dong, Manzhen Wang, Yuanyong Luo, Muhan Zheng, Mengyu An, Yajun Ha, Hongbing Pan:
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 2014-2027 (2020) - [c72]Rui Li, Heng Yu, Weixiong Jiang, Yajun Ha:
DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs. DAC 2020: 1-6 - [c71]Weixiong Jiang, Rui Li, Heng Yu, Yajun Ha:
An Accurate FPGA Online Delay Monitor Supporting All Timing Paths. ISCAS 2020: 1-5 - [c70]Yuqi Wang, Jian Chen, Yu Pu, Yajun Ha:
Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing. ISCAS 2020: 1-5 - [c69]Ruiqi Luo, Xiaolei Chen, Yajun Ha:
Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects. LASCAS 2020: 1-4 - [c68]Yi Wang, Dan Wei Ming Chia, Yajun Ha:
Vulnerability of Deep Learning Model based Anomaly Detection in Vehicle Network. MWSCAS 2020: 293-296
2010 – 2019
- 2019
- [j27]Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan:
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2156-2169 (2019) - [j26]Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan:
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2222 (2019) - [c67]Jian Chen, Wenfeng Zhao, Yajun Ha:
Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing. ASICON 2019: 1-4 - [c66]Weixiong Jiang, Heng Yu, Xinzhe Liu, Yajun Ha:
Energy Efficiency Optimization of FPGA-based CNN Accelerators with Full Data Reuse and VFS. ICECS 2019: 446-449 - [c65]Xinzhe Liu, Fupeng Chen, Yajun Ha:
Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree. ISVLSI 2019: 55-60 - [c64]Weixiong Jiang, Heng Yu, Yajun Ha:
Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC. SoCC 2019: 56-61 - [c63]Wenfeng Zhao, Biao Sun, Jian Chen, Yajun Ha:
AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design. SoCC 2019: 479-483 - 2018
- [j25]Tian Huang, Yongxin Zhu, Yajun Ha, Xu Wang, Meikang Qiu:
A Hardware Pipeline with High Energy and Resource Efficiency for FMM Acceleration. ACM Trans. Embed. Comput. Syst. 17(2): 51:1-51:20 (2018) - [c62]Yun Liang, Shuo Wang, Tulika Mitra, Yajun Ha:
Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications. ACA 2018: 95-108 - 2017
- [j24]Xu Wang, Yongxin Zhu, Yajun Ha, Meikang Qiu, Tian Huang, Xueming Si, Jiangxing Wu:
An energy-efficient system on a programmable chip platform for cloud applications. J. Syst. Archit. 76: 117-132 (2017) - [j23]Xu Wang, Yongxin Zhu, Yajun Ha, Meikang Qiu, Tian Huang:
An FPGA-Based Cloud System for Massive ECG Data Analysis. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 309-313 (2017) - [j22]Yi Wang, Yajun Ha:
A DFA-Resistant and Masked PRESENT with Area Optimization for RFID Applications. ACM Trans. Embed. Comput. Syst. 16(4): 102:1-102:22 (2017) - [c61]Wenfeng Zhao, Ang Li, Yi Wang, Yajun Ha:
Analysis and design of energy-efficient data-dependent SRAM. ASICON 2017: 912-915 - [c60]Heng Yu, Yajun Ha, Jing Wang:
Quality Optimization of Resilient Applications under Temperature Constraints. Conf. Computing Frontiers 2017: 9-16 - 2016
- [j21]Mengyao Zhu, Yajun Ha, Chengcun Gu, Liuchuang Gao:
An Optimized Logarithmic Converter With Equal Distribution of Relative Errors. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 848-852 (2016) - [c59]Chin Hau Hoo, Yajun Ha, Akash Kumar:
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. FPL 2016: 1-11 - [c58]Yi Wang, Yajun Ha:
High throughput and resource efficient AES encryption/decryption for SANs. ISCAS 2016: 1166-1169 - [c57]Yi Wang, Jianfeng An, Yajun Ha:
Unified data authenticated encryption for vehicular communication. MWSCAS 2016: 1-4 - [c56]Tian Huang, Yongxin Zhu, Yishu Mao, Xinyang Li, Mengyun Liu, Yafei Wu, Yajun Ha, Gillian Dobbie:
Parallel Discord Discovery. PAKDD (2) 2016: 233-244 - 2015
- [j20]Thi Hanh Nguyen, Yi Wang, Yajun Ha, Renfa Li:
Performance and security-enhanced fuzzy vault scheme based on ridge features for distorted fingerprints. IET Biom. 4(1): 29-39 (2015) - [j19]Ang Li, Akash Kumar, Yajun Ha, Henk Corporaal:
Correlation ratio based volume image registration on GPUs. Microprocess. Microsystems 39(8): 998-1011 (2015) - [j18]Guiyuan Jiang, Jigang Wu, Yajun Ha, Yi Wang, Jizhou Sun:
Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms. IEEE Trans. Computers 64(10): 2926-2939 (2015) - [j17]Wenfeng Zhao, Anastacia B. Alvarez, Yajun Ha:
A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 671-675 (2015) - [j16]Wenfeng Zhao, Yajun Ha, Massimo Alioto:
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1390-1401 (2015) - [c55]Yi Wang, Zhiqian Hong, Jun Li, Shaobo Luo, Yajun Ha:
Challenges and future trends for embedded security in electric vehicular communications. ASICON 2015: 1-4 - [c54]Chin Hau Hoo, Akash Kumar, Yajun Ha:
ParaLaR: A parallel FPGA router based on Lagrangian relaxation. FPL 2015: 1-6 - [c53]Wenfeng Zhao, Yajun Ha, Massimo Alioto:
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. ISCAS 2015: 2349-2352 - [i2]Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo:
TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs. CoRR abs/1506.03182 (2015) - 2014
- [j15]Yi Wang, Yajun Ha:
A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(2): 190-202 (2014) - [j14]Kejie Huang, Yajun Ha, Rong Zhao, Akash Kumar, Yong Lian:
A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2605-2613 (2014) - [c52]Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang:
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor. A-SSCC 2014: 301-304 - [c51]Heng Yu, Rizwan Syed, Yajun Ha:
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs. DATE 2014: 1-6 - [c50]Yi Wang, Akash Kumar, Yajun Ha:
FPGA-based high throughput XTS-AES encryption/decryption for storage area network. FPT 2014: 268-271 - [c49]Qiang Wu, Yajun Ha, Akash Kumar, Shaobo Luo, Ang Li, Shihab Mohamed:
A heterogeneous platform with GPU and FPGA for power efficient high performance computing. ISIC 2014: 220-223 - 2013
- [j13]Thi Hanh Nguyen, Yi Wang, Yajun Ha, Renfa Li:
Improved chaff point generation for vault scheme in bio-cryptosystems. IET Biom. 2(2): 48-55 (2013) - [j12]Heng Yu, Yajun Ha, Bharadwaj Veeravalli:
Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems. IEEE Trans. Computers 62(10): 2026-2040 (2013) - [j11]Yi Wang, Yajun Ha:
FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network. IEEE Trans. Circuits Syst. II Express Briefs 60-II(1): 36-40 (2013) - [c48]Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo:
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. ASP-DAC 2013: 320-325 - [c47]Heng Yu, Bharadwaj Veeravalli, Yajun Ha, Shaobo Luo:
Dynamic Scheduling of Imprecise-Computation Tasks on Real-Time Embedded Multiprocessors. CSE 2013: 770-777 - [c46]Zhi Ping Ang, Akash Kumar, Yajun Ha:
High Speed Video Processing Using Fine-Grained Processing on FPGA Platform. FCCM 2013: 85-88 - [c45]Chin Hau Hoo, Yajun Ha, Akash Kumar:
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm. FPL 2013: 1-4 - [c44]Wei Ting Loke, Wenfeng Zhao, Yajun Ha:
Criticality-based routing for FPGAS with reverse body bias switch box architectures. FPL 2013: 1-6 - [c43]Yi Wang, Yajun Ha:
FPGA based Rekeying for cryptographic key management in Storage Area Network. FPL 2013: 1-6 - [c42]Junsong Hou, Heng Yu, Yajun Ha, Xin Liu:
The architecture and placement algorithm for a uni-directional routing based 3D FPGA. FPT 2013: 28-33 - [c41]Yongzhen Chen, Miguel Rodel Felipe, Yi Wang, Yajun Ha, Shu Qin Ren, Khin Mi Mi Aung:
sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface. FPT 2013: 374-377 - [c40]Yi Wang, Yajun Ha:
An area-efficient shuffling scheme for AES implementation on FPGA. ISCAS 2013: 2577-2580 - [c39]Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez:
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. ISLPED 2013: 323-328 - 2012
- [j10]Rizwan Syed, Yajun Ha, Bharadwaj Veeravalli:
A low overhead abstract architecture for FPGA resource management. SIGARCH Comput. Archit. News 40(5): 28-33 (2012) - [c38]Wei Ting Loke, Yajun Ha:
A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters. ARC 2012: 174-186 - [c37]Wei Ting Loke, Yajun Ha:
Power-aware FPGA technology mapping for programmable-VT architectures (abstract only). FPGA 2012: 268 - [c36]Chao Wang, Xi Li, Xuehai Zhou, Yajun Ha:
Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs. FPT 2012: 53-56 - [c35]Wei Ting Loke, Yajun Ha, Wenfeng Zhao:
A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs. IPDPS Workshops 2012: 221-226 - 2011
- [c34]Wenjuan Zhang, Yajun Ha:
A Hilbert curve-based delay fault characterization method for FPGAs. ISCAS 2011: 2059-2062 - 2010
- [j9]Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. IEEE J. Solid State Circuits 45(3): 668-680 (2010) - [j8]Haiting Tian, Shakith Fernando, Hock Wei Soon, Zhang Qiang, Chunxi Zhang, Yajun Ha, Nanguang Chen:
Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array. IEEE Trans. Biomed. Circuits Syst. 4(1): 1-10 (2010) - [j7]Akash Kumar, Bart Mesman, Henk Corporaal, Yajun Ha:
Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 538-551 (2010) - [c33]Wenjuan Zhang, Shefali Srivastava, Yajun Ha:
B*-tree based variability-aware floorplanning. APCCAS 2010: 1191-1194 - [c32]Heng Yu, Bharadwaj Veeravalli, Yajun Ha:
Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems. DAC 2010: 493-498 - [c31]Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan, Yajun Ha:
Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA. FPT 2010: 365-368 - [c30]Zhiyao Joseph Yang, Akash Kumar, Yajun Ha:
An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee. FPT 2010: 389-392 - [c29]Heng Yu, Yajun Ha, Bharadwaj Veeravalli:
Communication-aware application mapping and scheduling for NoC-based MPSoCs. ISCAS 2010: 3232-3235 - [c28]Trang T. T. Do, Thinh M. Le, Binh P. Nguyen, Yajun Ha:
Performance-cost analyses software for H.264 Forward/Inverse Integer Transform. International Symposium on Rapid System Prototyping 2010: 1-7 - [e1]Jinian Bian, Qiang Zhou, Peter Athanas, Yajun Ha, Kang Zhao:
Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China. IEEE 2010, ISBN 978-1-4244-8981-7 [contents] - [i1]Xiaolei Chen, Yajun Ha:
The Optimization of Interconnection Networks in FPGAs. Dynamically Reconfigurable Architectures 2010
2000 – 2009
- 2009
- [c27]Pramod Kumar Meher, Yajun Ha, Chiou-Yng Lee:
An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials. ASP-DAC 2009: 210-215 - [c26]Guolei Zhu, Heng Yu, Yajun Ha, Yingmin Wang:
A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study. ERSA 2009: 267-270 - [c25]Rizwan Syed, Xiaolei Chen, Yajun Ha, Bharadwaj Veeravalli:
sFPGA2 - A scalable GALS FPGA architecture and design methodology. FPL 2009: 314-319 - [c24]Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply. ISSCC 2009: 146-147 - 2008
- [j6]Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha:
Analyzing composability of applications on MPSoC platforms. J. Syst. Archit. 54(3-4): 369-383 (2008) - [j5]Jenn-Yue Teo, Yajun Ha, Chen-Khong Tham:
Interference-Minimized Multipath Routing with Congestion Control in Wireless Sensor Network for High-Rate Streaming. IEEE Trans. Mob. Comput. 7(9): 1124-1137 (2008) - [j4]Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal:
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA. ACM Trans. Design Autom. Electr. Syst. 13(3): 40:1-40:27 (2008) - [c23]Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
Statistical noise margin estimation for sub-threshold combinational circuits. ASP-DAC 2008: 176-179 - [c22]Heng Yu, Bharadwaj Veeravalli, Yajun Ha:
Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems. ASP-DAC 2008: 452-455 - [c21]Hanyu Liu, Xiaolei Chen, Yajun Ha:
An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects. FCCM 2008: 275-276 - [c20]Shakith Fernando, Xiaolei Chen, Yajun Ha:
sFPGA - A scalable switch based FPGA architecture and design methodology. FPL 2008: 95-100 - [c19]Haiting Tian, Shakith Fernando, Hock Wei Soon, Yajun Ha, Nanguang Chen:
Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA. FPL 2008: 583-586 - [c18]Hanyu Liu, Xiaolei Chen, Yajun Ha:
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. FPL 2008: 615-618 - [c17]Fujie Wong, Yajun Ha:
A low overhead fault tolerant FPGA with new connection box. FPL 2008: 643-646 - [c16]Yanhui Li, Shakith Fernando, Heng Yu, Xiaolei Chen, Yajun Ha, Teng Tiow Tay:
Tighter WCET analysis of input dependent programs with classified-cache memory architecture. ICECS 2008: 410-413 - 2007
- [c15]Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha:
A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. DAC 2007: 726-731 - [c14]Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal:
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. FPL 2007: 92-97 - [c13]Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, Yajun Ha:
Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools. FPL 2007: 279-284 - [c12]Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
Vt balancing and device sizing towards high yield of sub-threshold static logic gates. ISLPED 2007: 355-358 - 2006
- [c11]Yu Pu, Yajun Ha:
An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model. ASP-DAC 2006: 886-891 - [c10]Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha:
Global Analysis of Resource Arbitration for MPSoC. DSD 2006: 71-78 - [c9]Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha:
Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. ESTIMedia 2006: 33-38 - 2005
- [j3]Yung Han Tan, Arun Krishnan Thampi, Daley Joseph Sebastian, Yajun Ha:
Design of Seamless Protocol Switching Layer for Voice Over Internet Protocol (Voip) That Switches Between Bluetooth and Ieee 802.11. Int. J. Softw. Eng. Knowl. Eng. 15(2): 271-278 (2005) - [j2]Jia Hui Ng, Chaur Lih Tan, Yajun Ha:
An Embedded System to Support Tele-Medical Activity. Int. J. Softw. Eng. Knowl. Eng. 15(2): 279-288 (2005) - [c8]Shakith Fernando, Yajun Ha:
Design of Networked Reconfigurable Encryption Engine. FCCM 2005: 285-286 - 2002
- [j1]Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Rudy Lauwereins, Hugo De Man:
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. J. Supercomput. 21(2): 131-144 (2002) - [c7]Yajun Ha, Radovan Hipik, Serge Vernalde, Diederik Verkest, Marc Engels, Rudy Lauwereins, Hugo De Man:
Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. FPL 2002: 1135-1138 - 2001
- [c6]Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man:
Virtual Java/FPGA interface for networked reconfiguration. ASP-DAC 2001: 558-563 - [c5]Yajun Ha, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man:
A SW/HW Interface API for Java/FPGA Co-Designed Applets. FCCM 2001: 269-270 - [c4]Yajun Ha, Bingfeng Mei, Patrick Schaumont, Serge Vernalde, Rudy Lauwereins, Hugo De Man:
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. FPL 2001: 264-274 - 2000
- [c3]Yajun Ha, Serge Vernalde, Patrick Schaumont, Marc Engels, Hugo De Man:
Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. PDPTA 2000 - [c2]Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man:
A Hardware Virtual Machine for the Networked Reconfiguration. IEEE International Workshop on Rapid System Prototyping 2000: 194-199
1990 – 1999
- 1999
- [c1]Yajun Ha, M. F. Li, Ai Qun Liu:
Low-voltage high driving capability CMOS buffer used in MEMS interface circuits. ICECS 1999: 1313-1316
Coauthor Index
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