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Luc Rijnders
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2010 – 2019
- 2016
- [c10]Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean:
Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC 2016: 131-134
2000 – 2009
- 2006
- [c9]Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo:
System Level Architecture Exploration for Reconfigurable Systems On Chip. FPL 2006: 1-6 - 2003
- [c8]Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor:
Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java. SCOPES 2003: 313-328 - 2001
- [j2]Robert Pasko, Luc Rijnders, Patrick R. Schaumont, Serge A. Vernalde, Daniela Duracková:
High-performance flexible all-digital quadrature up and down converter chip. IEEE J. Solid State Circuits 36(3): 408-416 (2001) - 2000
- [c7]Robert Pasko, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Daniela Duracková:
High-performance flexible all-digital quadrature up and down converter chip. CICC 2000: 43-46 - [c6]Yajun Ha, Patrick Schaumont
, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man:
A Hardware Virtual Machine for the Networked Reconfiguration. IEEE International Workshop on Rapid System Prototyping 2000: 194-199
1990 – 1999
- 1999
- [c5]Radim Cmar, Luc Rijnders, Patrick Schaumont
, Serge Vernalde, Ivo Bolsens:
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement. DATE 1999: 271- - 1998
- [c4]Patrick Schaumont
, Serge Vernalde, Luc Rijnders, Marc Engels
, Ivo Bolsens:
A Programming Environment for the Design of Complex High Speed ASICs. DAC 1998: 315-320 - 1997
- [c3]Patrick Schaumont
, Serge Vernalde, Luc Rijnders, Marc Engels
, Ivo Bolsens:
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. ED&TC 1997: 542-546 - 1995
- [c2]Luc Rijnders, Zohair Sahraoui, Paul Six, Hugo De Man:
Timing optimization by bit-level arithmetic transformations. EURO-DAC 1995: 48-53
1980 – 1989
- 1989
- [j1]I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man:
REDUSA: module generation by automatic elimination of superfluous blocks in regular structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(9): 989-998 (1989) - [c1]I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man:
REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures. DAC 1989: 694-697
Coauthor Index
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