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Mohamed Badr Younis

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affiliation: University of Illinois at Urbana-Champaign, Urbana, IL, USA

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2020 – today

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2024
[c4]
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  - conf/isscc/KhalilYXAWPH24
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Mahmoud A. Khalil, Mohamed Badr Younis, Ruhao Xia, Ahmed E. AbdelRahman, Tianyu Wang, Kyu-Sang Park, Pavan Kumar Hanumolu:
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise. ISSCC 2024: 138-140
2023
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Yongxin Li, Nilanjan Pal, Tianyu Wang, Mostafa Gamal Ahmed, Ahmed E. AbdelRahman, Mohamed Badr Younis, Kyu-Sang Park, Ruhao Xia, Pavan Kumar Hanumolu:
A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator. IEEE J. Solid State Circuits 58(3): 785-795 (2023)
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Ahmed E. AbdelRahman, Mostafa Gamal Ahmed, Mahmoud A. Khalil, Mohamed Badr Younis, Kyu-Sang Park, Pavan Kumar Hanumolu:
A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver. ISSCC 2023: 208-209
[c2]
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Mohamed Badr Younis, Mostafa Gamal Ahmed, Tianyu Wang, Ahmed E. AbdelRahman, Mahmoud A. Khalil, Anup P. Jose, Pavan Kumar Hanumolu:
A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop. VLSI Technology and Circuits 2023: 1-2
2022
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Yongxin Li, Nilanjan Pal, Tianyu Wang, Mostafa Gamal Ahmed, Ahmed E. AbdelRahman, Mohamed Badr Younis, Ruhao Xia, Kyu-Sang Park, Pavan Kumar Hanumolu:
A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy. CICC 2022: 1-2

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