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2020 – today
- 2024
[j40]Yuqiang Cui
, Weiwei Shan, Peng Cao:
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS. Integr. 94: 102094 (2024)- [j39]Cai Li, Haochang Zhi, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Chao Chen, Xi Wang, Weiwei Shan:
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN. IEEE J. Solid State Circuits 59(3): 867-877 (2024) - [j38]Yuxuan Du, Junyi Qian, Zhengguo Shen, Chengjun Wu, Weiwei Shan, Xi Wang:
DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits. IEEE J. Solid State Circuits 59(7): 2286-2296 (2024) - [j37]Jintao Li, Yanhan Zeng, Haochang Zhi, Jingci Yang, Weiwei Shan, Yongfu Li, Yun Li:
Knowledge Transfer Framework for PVT Robustness in Analog Integrated Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 71(5): 2017-2030 (2024) - [j36]Yuqiang Cui, Lishuo Deng, Keran Li, Weiwei Shan:
FLC-EDC: A Fast Low-Cost Error Detection and Correction Scheme for AVFS System Based on Flip-Flops Resampling in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 390-394 (2024) - [c49]Yuchen Hu, Ke Xu, Jialin Sun, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang:
Make Each Iteration Count. ACM TUR-C 2024 - [c48]Lishuo Deng, Zhengguo Shen, Zhuo Chen, Cai Li, Junyi Qian, Yuxuan Du, Kaize Zhou, Keran Li, Ruidong Li, Tuo Li, Xiaofeng Zou, Weiwei Shan:
An Adaptive Wide-Voltage-Range Droop Detection and Protection System Assisted with Timing Error Detection in 28nm CMOS. CICC 2024: 1-2 - [c47]Weiwei Shan, Kaize Zhou, Keran Li, Yuxuan Du, Zhuo Chen, Junyi Qian, Haitao Ge, Jun Yang, Xin Si:
14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS. ISSCC 2024: 256-258 - [c46]An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si:
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. ISSCC 2024: 570-572 - [i2]Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang:
MEIC: Re-thinking RTL Debug Automation using LLMs. CoRR abs/2405.06840 (2024) - [i1]Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng:
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. CoRR abs/2409.08534 (2024) - 2023
- [j35]Weiwei Shan, Yuqiang Cui, Wentao Dai, Xinning Liu, Jingjing Guo, Peng Cao, Jun Yang:
An efficient path delay variability model for wide-voltage-range digital circuits. Sci. China Inf. Sci. 66(2) (2023) - [j34]Zhuo Chen, Yuxuan Du, Boyang Cheng, Weiwei Shan:
Design of high-efficiency complex multiplier for fault-tolerant computation. Integr. 90: 190-195 (2023) - [j33]Weiwei Shan, Junyi Qian, Lixuan Zhu, Jun Yang, Cheng Huang, Hao Cai:
AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS. IEEE J. Solid State Circuits 58(3): 867-876 (2023) - [j32]Zhengguo Shen, Weiwei Shan, Yuxuan Du, Ziyu Li, Jun Yang:
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss. IEEE J. Solid State Circuits 58(5): 1462-1471 (2023) - [j31]Yuxuan Du, Zhuo Chen, Boyang Cheng, Weiwei Shan:
Design and analysis of leading one/zero detector based approximate multipliers. Microelectron. J. 136: 105783 (2023) - [j30]Yuxuan Du, Junyi Qian, Zhuo Chen, Weiwei Shan:
An All-Digital, 1.92-7.32 mV/LSB, 0.5-2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS System. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4888-4899 (2023) - [j29]Long Chen, Cai Li, Tao Wang, Junyi Qian, Weiwei Shan:
A 1.23μJ/Inference, All-Digital Shuffle-Type Group-CNN Accelerator in 28nm CMOS With 85.8% Accuracy on CIFAR-10. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 296-300 (2023) - [c45]Zhengguo Shen, Junyi Qian, Keran Li, Ziyu Li, Lishuo Deng, Weiwei Shan:
TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS. A-SSCC 2023: 1-3 - [c44]Yuxuan Du, Haitao Ge, Zhuo Chen, Kaize Zhou, Zhengguo Shen, Weiwei Shan:
A 28nm All-Digital, 1.92-7.32mV/LSB, 0.5-2GS/s sample rate, 0-latency Voltage Sensor with Dynamic PVT Calibration for Wide-range Adaptive Voltage Scaling. CICC 2023: 1-2 - [c43]Cai Li, Haochang Zhi, Long Chen, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Weiwei Shan:
A 608nW Near-Microphone Keyword-Spotting Chip Using Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN in 28nm CMOS. CICC 2023: 1-2 - [c42]Jintao Li, Haochang Zhi, Weiwei Shan, Yongfu Li, Yanhan Zeng, Yun Li:
Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization. ICCAD 2023: 1-9 - [c41]Yizhi Ding, Haochang Zhi, Jintao Li, Zhuo Chen, Kaiyue Yang, Weiwei Shan:
A Compact and Robust 28nm CMOS Temperature Sensor with Machine Learning Assisted Design for DVFS SoC. ICTA 2023: 87-88 - [c40]Lishuo Deng, Keran Li, Weiwei Shan:
IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits. ISCAS 2023: 1-5 - [c39]An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang:
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. ISSCC 2023: 128-129 - [c38]Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan:
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. ISSCC 2023: 500-501 - 2022
- [j28]Ruixin Mao, Sixu Li, Zhaomin Zhang, Zihan Xia, Jianbiao Xiao, Zixuan Zhu, Jiahao Liu, Weiwei Shan, Liang Chang, Jun Zhou:
An Ultra-Energy-Efficient and High Accuracy ECG Classification Processor With SNN Inference Assisted by On-Chip ANN Learning. IEEE Trans. Biomed. Circuits Syst. 16(5): 832-841 (2022) - [c37]Yuqiang Cui, Weiwei Shan:
A High-Precision PVT-Tolerance Adaptive Clock Circuit Over Wide Frequencies in 28nm CMOS. APCCAS 2022: 256-259 - [c36]Jiahao Liu, Jianbiao Xiao, Jiajing Fan, Qingsong Liu, Zixuan Zhu, Sixu Li, Zhaomin Zhang, Siqi Yang, Weiwei Shan, Shuisheng Lin, Liang Chang, Liang Zhou, Jun Zhou:
An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-Up. CICC 2022: 1-2 - [c35]Jiahao Liu, Zirui Zhong, Yong Zhou, Hui Qiu, Jianbiao Xiao, Jiajing Fan, Zhaomin Zhang, Sixu Li, Yiming Xu, Siqi Yang, Weiwei Shan, Shuisheng Lin, Liang Chang, Jun Zhou:
An energy-efficient seizure detection processor using event-driven multi-stage CNN classification and segmented data processing with adaptive channel selection. DAC 2022: 217-222 - [c34]Haitao Ge, Weiwei Shan, Yicheng Lu, Jun Yang:
A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation. ICTA 2022: 98-99 - [c33]Kaize Zhou, Dejian Li, Chongfei Shen, Yuxuan Du, Zhuo Chen, Weiwei Shan:
A Voltage Error Quantizer For Digital Low Dropout Regulators With Fast Transient Response and Low Steady-State Error. ICTA 2022: 102-103 - 2021
- [j27]Weiwei Shan, Minhao Yang, Tao Wang, Yicheng Lu, Hao Cai, Lixuan Zhu, Jiaming Xu, Chengjun Wu, Longxing Shi, Jun Yang:
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS. IEEE J. Solid State Circuits 56(1): 151-164 (2021) - [j26]Minhao Yang, Hongjie Liu, Weiwei Shan, Jun Zhang, Ilya Kiselev, Sang Joon Kim, Christian C. Enz, Mingoo Seok:
Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction. IEEE J. Solid State Circuits 56(10): 3123-3133 (2021) - [j25]Zhikuang Cai, Boyang Cheng, Yuxuan Du, Xinchao Shang, Weiwei Shan:
A Time-Domain Binary CNN Engine With Error-Detection-Based Resilience in 28nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3177-3181 (2021) - [c32]Ziyu Li, Weiwei Shan, Chengjun Wu, Haitao Ge, Jun Yang:
An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS. A-SSCC 2021: 1-3 - [c31]Lixuan Zhu, Weiwei Shan, Jiaming Xu, Yicheng Lu:
AAD-KWS: a sub-µW keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS. ESSCIRC 2021: 99-102 - [c30]Lixuan Zhu, Weiwei Shan, Jiaming Xu, Yicheng Lu:
AAD-KWS: a sub-$\mu\mathrm{W}$ keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS. ESSDERC 2021: 99-102 - [c29]Kaiyue Yang, Lixuan Zhu, Weiwei Shan:
Design of an ultra-low Power MFCC Feature Extraction Circuit with Embedded Speech Activity Detector. ICTA 2021: 82-83 - [c28]Yuqiang Cui, Chengjun Wu, Ziyu Li, Weiwei Shan:
Energy-Efficient Design of Large Fan-in Dynamic One-hot Multiplexer in 28nm CMOS Technology. ICTA 2021: 197-198 - 2020
- [j24]Weiwei Shan, Shuai Zhang, Jiaming Xu, Minyi Lu, Longxing Shi, Jun Yang:
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit. IEEE J. Solid State Circuits 55(3): 794-804 (2020) - [j23]Weiwei Shan, Wentao Dai, Liang Wan, Minyi Lu, Longxing Shi, Mingoo Seok, Jun Yang:
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System. IEEE J. Solid State Circuits 55(3): 826-836 (2020) - [j22]Weiwei Shan, Wentao Dai, Chuan Zhang, Hao Cai, Peiye Liu, Jun Yang, Longxing Shi:
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS. IEEE J. Solid State Circuits 55(5): 1422-1436 (2020) - [j21]Xinchao Shang, Minyi Lu, Chengjun Wu, Yiming Xiang, Jiaming Xu, Weiwei Shan:
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS. IEEE Trans. Circuits Syst. 67-I(11): 3933-3943 (2020) - [c27]Yuxuan Du, Xinchao Shang, Weiwei Shan:
An Energy-Efficient Time-Domain Binary Neural Network Accelerator with Error-Detection in 28nm CMOS. APCCAS 2020: 70-73 - [c26]Lixuan Zhu, Lixing Li, Weiwei Shan:
Design of Approximate Complex Constant Multiplier for Fast Fourier Transform in 28nm CMOS. ICTA 2020: 81-82 - [c25]Martin Shan, Daniel Duckwitz, Weiwei Shan:
Using Wind Turbines for Providing Defined Levels of Synthetic Inertia in System Split Scenarios. ISGT-Europe 2020: 829-833 - [c24]Weiwei Shan, Minhao Yang, Jiaming Xu, Yicheng Lu, Shuai Zhang, Tao Wang, Jun Yang, Longxing Shi, Mingoo Seok:
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS. ISSCC 2020: 230-232
2010 – 2019
- 2019
- [j20]Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao:
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 239-250 (2019) - [j19]Weiwei Shan, Xinchao Shang, Xing Wan, Hao Cai, Chuan Zhang, Jun Yang:
A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2288-2297 (2019) - [c23]Yicheng Lu, Weiwei Shan, Jiaming Xu:
A Depthwise Separable Convolution Neural Network for Small-footprint Keyword Spotting Using Approximate MAC Unit and Streaming Convolution Reuse. APCCAS 2019: 309-312 - [c22]Weiwei Shan, Shogo Muramatsu, Akira Oshima, Hiroyoshi Yamada:
Successive Stripe Artifact Removal Based on Robust PCA for Millimeter Wave Automotive Radar Image. APSIPA 2019: 1391-1394 - [c21]Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao:
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. ACM Great Lakes Symposium on VLSI 2019: 135-140 - [c20]Tao Wang, Weiwei Shan:
An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing. NANOARCH 2019: 1-6 - [c19]Chengjun Wu, Weiwei Shan, Jiaming Xu:
ynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience. NANOARCH 2019: 1-6 - [c18]Weiwei Shan, Ao Fan, Jiaming Xu, Jun Yang, Mingoo Seok:
A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS. VLSI Circuits 2019: 236- - 2018
- [j18]Weiwei Shan, Xinning Liu, Minyi Lu, Liang Wan, Jun Yang:
A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits. IEEE Access 6: 138-145 (2018) - [j17]Xinchao Shang, Weiwei Shan, Xinning Liu:
Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures. J. Circuits Syst. Comput. 27(11): 1850180:1-1850180:20 (2018) - [j16]Weiwei Shan, Xinchao Shang, Longxing Shi, Wentao Dai, Jun Yang:
Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 933-937 (2018) - [j15]Weiwei Shan, Liang Wan, Xinning Liu, Xinchao Shang, Wentao Dai, Shuai Shao, Jun Yang, Longxing Shi:
A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1718-1722 (2018) - [j14]Wentao Dai, Weiwei Shan, Xinchao Shang, Xinning Liu, Hao Cai, Jun Yang:
HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3907-3917 (2018) - [c17]Xinchao Shang, Weiwei Shan, Jiaming Xu, Minyi Lu, Yiming Xiang, Longxing Shi, Jun Yang:
A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator. A-SSCC 2018: 1-4 - [c16]Wentao Dai, Peiye Liu, Weiwei Shan:
Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion. ACM Great Lakes Symposium on VLSI 2018: 105-110 - [c15]Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Weiwei Shan, Jun Yang, Weisheng Zhao:
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. ISCAS 2018: 1-5 - [c14]Minyi Lu, Ao Fan, Jiaming Xu, Weiwei Shan:
A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS. TrustCom/BigDataSE 2018: 1464-1469 - [c13]Jiaming Xu, Ao Fan, Minyi Lu, Weiwei Shan:
Differential Power Analysis of 8-Bit Datapath AES for IoT Applications. TrustCom/BigDataSE 2018: 1470-1473 - [c12]Aiguo Bu, Wentao Dai, Minyi Lu, Hao Cai, Weiwei Shan:
Correlation-Based Electromagnetic Analysis Attack Using Haar Wavelet Reconstruction with Low-Pass Filtering on an FPGA Implementaion of AES. TrustCom/BigDataSE 2018: 1897-1900 - 2017
- [j13]Weiwei Shan, Longxing Shi, Jun Yang:
In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications. IEEE Access 5: 15831-15838 (2017) - [j12]Weiwei Shan, Xinning Liu, Minyi Lu, Shuai Shao, Zhikuang Cai, Jun Yang:
An improved timing error prediction monitor for wide adaptive frequency scaling. IEICE Electron. Express 14(21): 20170808 (2017) - [c11]Xinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang:
A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications. A-SSCC 2017: 205-208 - [c10]Wentao Dai, Weiwei Shan, Xinning Liu, Jun Yang:
HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS. A-SSCC 2017: 209-212 - 2016
- [j11]Weiwei Shan, Wentao Dai, Youhua Shi, Peng Cao, Xiaoyan Xiang:
Timing monitoring paths selection for wide voltage IC. IEICE Electron. Express 13(8): 20160095 (2016) - 2015
- [j10]Weiwei Shan, Xingyuan Fu, Zhipeng Xu:
A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1201-1205 (2015) - 2014
- [j9]Weiwei Shan, Xiao Zhang, Xingyuan Fu, Peng Cao:
VLSI design of a reconfigurable S-box based on memory sharing method. IEICE Electron. Express 11(1): 20130872 (2014) - [c9]Weiwei Shan, Zhipeng Xu:
Timing error prediction based adaptive voltage scaling for dynamic variation tolerance. APCCAS 2014: 739-742 - [c8]Weiwei Shan, Longxing Shi, Xingyuan Fu, Xiao Zhang, Chaoxuan Tian, Zhipeng Xu, Jun Yang, Jie Li:
A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms. DAC 2014: 176:1-176:6 - 2013
- [j8]Weiwei Shan, Haolin Gu, Bo Li, Xiaoqing Wu, Haikun Jin, Yintao Guo, Peng Cao:
An improved timing monitor for deep dynamic voltage scaling system. IEICE Electron. Express 10(6): 20130089 (2013) - [j7]Xin Chen, Ning Wu, Wei Hu, Weiwei Shan:
BIST design of power switch. IEICE Electron. Express 10(15): 20130469 (2013) - [j6]Zhikuang Cai, Haobo Xu, Shixuan Que, Weiwei Shan, Jun Yang:
On-chip long-term jitter measurement for PLL based on undersampling technique. IEICE Electron. Express 10(24): 20130887 (2013) - [j5]Jun Yang, Weiwei Shan, Junyin Liu, Huafang Sun:
Implementation of correlation power analysis attack on an FPGA DES design. Int. J. Inf. Commun. Technol. 5(3/4): 296-306 (2013) - [j4]Weiwei Shan, Xin Chen, Bo Li, Peng Cao, Jie Li, Gugang Gao, Longxing Shi:
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware. IEEE Trans. Instrum. Meas. 62(10): 2716-2724 (2013) - 2012
- [c7]Peng Cao, Huiyan Jiang, Bo Liu, Weiwei Shan:
Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture. CyberC 2012: 228-231 - [c6]Xuexiang Wang, Weiwei Shan, Hao Liu:
Uniform SystemC Co-Simulation Methodology for System-on-Chip Designs. CyberC 2012: 261-267 - [c5]Peng Cao, Yong Cai, Bo Liu, Weiwei Shan:
Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array. CyberC 2012: 286-291 - [c4]Jie Li, Xinxiang Ke, Peng Cao, Weiwei Shan:
A New Approach to Implement Discrete Wavelet Transform on Coarse-Grained Reconfigurable Architecture. CyberC 2012: 292-297 - [c3]Jie Li, Yuxiang Lv, Huafang Sun, Weiwei Shan:
A Power Analysis Resistant DES Cryptographic Algorithm and Its Hardware Design. ICDMA 2012: 121-124 - 2011
- [j3]Weiwei Shan, Xin Chen:
A Novel Combined Proportional-Derivative Control for Electrostatic MEMS Mirror Actuation. IEICE Trans. Electron. 94-C(9): 1486-1489 (2011)
2000 – 2009
- 2009
- [j2]Weiwei Shan, Yan Liang, Dongming Jin:
Cmos Circuit Design of a Takagi-Sugeno Fuzzy Logic Controller. J. Circuits Syst. Comput. 18(4): 841-856 (2009) - [c2]Weiwei Shan, Xiqun Zhu, Yuan Ma:
Adaptive Fuzzy Logic Controller and Its Application in MEMS Mirror Actuation Feedback Control. IDEAL 2009: 74-81 - 2008
- [j1]Weiwei Shan, Yuan Ma, Robert W. Newcomb, Dongming Jin:
Analog Circuit Implementation of a Variable Universe Adaptive Fuzzy Logic Controller. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 976-980 (2008) - 2005
- [c1]Weiwei Shan, Dongming Jin, Weiwei Jin, Zhihao Xu:
VLSI Implementation of a Self-tuning Fuzzy Controller Based on Variable Universe of Discourse. FSKD (1) 2005: 1044-1052
Coauthor Index
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