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2020 – today
- 2023
[c39]Jiaxiang Li, Masao Yanagisawa, Youhua Shi:
An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators. ASICON 2023: 1-4- [c38]Yirui Su, Masao Yanagisawa, Youhua Shi:
Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators. ICICDT 2023: 131-135 - 2021
- [j20]Lin Ye, Jinghao Ye
, Masao Yanagisawa, Youhua Shi:
Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow. IEEE Access 9: 17411-17420 (2021) - [c37]Qianjin Wang, Yi Zhan, Bingqiang Liu, Jiajun Wu, Youhua Shi, Guoyi Yu, Chao Wang:
A Reconfigurable Area and Energy Efficient Hardware Accelerator of Five High-order Operators for Vision Sensor Based Robot Systems. ICTA 2021: 189-190 - 2020
- [j19]Jinghao Ye, Masao Yanagisawa, Youhua Shi:
Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(9): 1063-1070 (2020) - [j18]Saki Tajima, Masao Yanagisawa, Youhua Shi:
Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets. IEEE Trans. Circuits Syst. II Express Briefs 67-II(6): 1114-1118 (2020) - [c36]Jinghao Ye, Masao Yanagisawa, Youhua Shi:
A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. APCCAS 2020: 121-124
2010 – 2019
- 2019
- [c35]Jinghao Ye, Masao Yanagisawa, Youhua Shi:
A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. APCCAS 2019: 29-32 - [c34]Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi:
A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks. APCCAS 2019: 317-320 - [c33]Jinghao Ye, Masao Yanagisawa, Youhua Shi:
An Adder-Segmentation-based FIR for High Speed Signal Processing. ASICON 2019: 1-4 - [c32]Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. ISCAS 2019: 1-4 - 2018
- [j17]Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1014-1024 (2018) - [j16]Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(7): 1025-1034 (2018) - [c31]Kento Hasegawa, Youhua Shi, Nozomu Togawa:
Hardware Trojan Detection Utilizing Machine Learning Approaches. TrustCom/BigDataSE 2018: 1891-1896 - 2017
- [c30]Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi:
Soft error tolerant latch designs with low power consumption (invited paper). ASICON 2017: 52-55 - [c29]Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
A low cost and high speed CSD-based symmetric transpose block FIR implementation. ASICON 2017: 311-314 - 2016
- [j15]Weiwei Shan, Wentao Dai, Youhua Shi, Peng Cao, Xiaoyan Xiang:
Timing monitoring paths selection for wide voltage IC. IEICE Electron. Express 13(8): 20160095 (2016) - [c28]Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A delay variation and floorplan aware high-level synthesis algorithm with body biasing. ISQED 2016: 75-80 - [c27]Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
In-situ Trojan authentication for invalidating hardware-Trojan functions. ISQED 2016: 152-157 - 2015
- [j14]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1376-1391 (2015) - [j13]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1406-1418 (2015) - [j12]Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa:
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2537-2546 (2015) - [c26]Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
A low-power soft error tolerant latch scheme. ASICON 2015: 1-4 - [c25]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. ASICON 2015: 1-4 - [c24]Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A score-based classification method for identifying hardware-trojans at gate-level netlists. DATE 2015: 465-470 - [c23]Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. SoCC 2015: 7-12 - 2014
- [c22]Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. APCCAS 2014: 300-303 - [c21]Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Secure scan design using improved random order and its evaluations. APCCAS 2014: 555-558 - [c20]Youhua Shi, Nozomu Togawa:
In-situ timing monitoring methods for variation-resilient designs. APCCAS 2014: 735-738 - [c19]Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Throughput driven check point selection in suspicious timing error prediction based designs. LASCAS 2014: 1-4 - 2013
- [j11]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2597-2611 (2013) - [c18]Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. ISCAS 2013: 1432-1435 - [c17]Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa:
Suspicious timing error prediction with in-cycle clock gating. ISQED 2013: 335-340 - [c16]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Secure Scan Design with Dynamically Configurable Connection. PRDC 2013: 256-262 - [c15]Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa:
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT 2013: 1-4 - 2012
- [j10]Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures. IEICE Electron. Express 9(17): 1414-1422 (2012) - [j9]Youhua Shi, Nozomu Togawa, Masao Yanagisawa:
Scan-Based Attack on AES through Round Registers and Its Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2338-2346 (2012) - [j8]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 176-181 (2012) - [c14]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. APCCAS 2012: 607-610 - [c13]Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa:
Dynamically changeable secure scan architecture against scan-based side channel attack. ISOCC 2012: 155-158 - 2010
- [j7]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1294-1299 (2010) - [c12]Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS 2010: 1139-1142 - [c11]Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS 2010: 1867-1870
2000 – 2009
- 2009
- [j6]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(9): 2304-2317 (2009) - [j5]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3119-3127 (2009) - [c10]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Design-for-secure-test for crypto cores. ITC 2009: 1 - 2008
- [j4]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. 91-D(3): 776-780 (2008) - [j3]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3514-3523 (2008) - [c9]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Unknown response masking with minimized observable response loss and mask data. APCCAS 2008: 1779-1781 - [c8]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
GECOM: Test data compression combined with all unknown response masking. ASP-DAC 2008: 577-582 - [c7]Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). ASP-DAC 2008: 697-702 - 2007
- [c6]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS 2007: 149-152 - 2006
- [j2]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 996-1004 (2006) - [c5]Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC 2006: 653-658 - [c4]Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito:
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT 2006: 136-144 - 2005
- [c3]Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura:
Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium 2005: 386-389 - 2004
- [c2]Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium 2004: 432-437 - 2003
- [j1]Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki:
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3056-3062 (2003) - [c1]Youhua Shi, Zhe Zhang:
Multiple test set generation method for LFSR-based BIST. ASP-DAC 2003: 863-868
Coauthor Index
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