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2020 – today
- 2024
[j32]Wenbo Guo
, Shuguo Li:
Split-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber. IEEE Trans. Computers 73(1): 97-108 (2024)- [j31]Tianqi Kong, Shuguo Li:
Hardware Acceleration and Implementation of Fully Homomorphic Encryption Over the Torus. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1116-1129 (2024) - [j30]Liang Kong, Guojie Qin, Shuguo Li:
Design an Efficient FPGA-Based Accelerator for Leveled BFV Homomorphic Encryption. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1381-1385 (2024) - 2023
- [j29]Wenbo Guo, Shuguo Li:
Highly-Efficient Hardware Architecture for CRYSTALS-Kyber With a Novel Conflict-Free Memory Access Pattern. IEEE Trans. Circuits Syst. I Regul. Pap. 70(11): 4505-4515 (2023) - 2022
- [j28]Zhen Gu, Shuguo Li:
Optimized Interpolation of Four-Term Karatsuba Multiplication and a Method of Avoiding Negative Multiplicands. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1199-1209 (2022) - [j27]Wenbo Guo, Shuguo Li, Liang Kong:
An Efficient Implementation of KYBER. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1562-1566 (2022) - 2021
- [j26]Liang Kong, Shuguo Li, Ruirui Liu:
High-Performance Constant-Time Discrete Gaussian Sampling. IEEE Trans. Computers 70(7): 1019-1033 (2021) - [j25]Yufei Xing, Shuguo Li:
A Compact Hardware Implementation of CCA-Secure Key Exchange Mechanism CRYSTALS-KYBER on FPGA. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(2): 328-356 (2021) - [j24]Wenbo Guo, Shuguo Li:
Fast Binary Counters and Compressors Generated by Sorting Network. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1220-1230 (2021) - [j23]Tianqi Kong, Shuguo Li:
Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 29(10): 1771-1781 (2021) - [c23]Shuguo Li, Wenbo Guo:
Area-Efficient Modular Reduction Structure and Memory Access Scheme for NTT. ISCAS 2021: 1-5 - [c22]Jinpeng Lu, Shuguo Li:
A Multibit Left-Shift Modular Inverse Hardware Algorithm and its Implementation. ISCAS 2021: 1-5 - 2020
- [j22]Xiang Feng, Shuguo Li, Sufen Xu:
RLWE-Oriented High-Speed Polynomial Multiplier Utilizing Multi-Lane Stockham NTT Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 556-559 (2020) - [j21]Yufei Xing, Shuguo Li:
An Efficient Implementation of the NewHope Key Exchange on FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 866-878 (2020) - [j20]Jinnan Ding, Shuguo Li:
A Low-Latency and Low-Cost Montgomery Modular Multiplier Based on NLP Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1319-1323 (2020) - [c21]Zhen Gu, Shuguo Li:
A Novel Method of Modular Multiplication Based on Karatsuba-like Multiplication. ARITH 2020: 33-40 - [c20]Yating Du, Shuguo Li:
A Binary Counter Based on Stacking and Sorting. ICCE 2020: 1-2 - [c19]Qing Liao, Shuguo Li:
A New Implementation of 16-bit Parallel Prefix Adder for High Speed and Low Area. ICDSP 2020: 284-288 - [c18]Yimeng Chen, Shuguo Li:
A High-Throughput Hardware Implementation of SHA-256 Algorithm. ISCAS 2020: 1-4
2010 – 2019
- 2019
- [j19]Zhen Gu, Shuguo Li:
A Generalized RNS Mclaughlin Modular Multiplication with Non-Coprime Moduli Sets. IEEE Trans. Computers 68(11): 1689-1696 (2019) - [j18]Xiang Feng, Shuguo Li:
Accelerating an FHE Integer Multiplier Using Negative Wrapped Convolution and Ping-Pong FFT. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 121-125 (2019) - [j17]Jinnan Ding, Shuguo Li, Zhen Gu:
High-Speed ECC Processor Over NIST Prime Fields Applied With Toom-Cook Multiplication. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1003-1016 (2019) - [j16]Zhen Gu, Shuguo Li:
A Division-Free Toom-Cook Multiplication-Based Montgomery Modular Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 66-II(8): 1401-1405 (2019) - [c17]Ruirui Liu, Shuguo Li:
A Design and Implementation of Montgomery Modular Multiplier. ISCAS 2019: 1-4 - 2018
- [j15]Lijuan Li, Shuguo Li:
Improved Algorithms and Implementations for Integer to τ NAF Conversion for Koblitz Curves. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1): 154-162 (2018) - [j14]Jinnan Ding, Shuguo Li:
A Modular Multiplier Implemented With Truncated Multiplication. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1713-1717 (2018) - [j13]Lijuan Li, Shuguo Li:
High-Performance Pipelined Architecture of Point Multiplication on Koblitz Curves. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1723-1727 (2018) - [c16]Shuguo Li, Zhen Gu:
Lazy Reduction and Multi-Precision Division Based on Modular Reductions. APCCAS 2018: 407-410 - [c15]Zhen Gu, Shuguo Li:
An Implementation of Karatsuba-based Montgomery Modular Multiplication with Only Half-size Additions. ISCAS 2018: 1-5 - 2017
- [j12]Xiang Feng, Shuguo Li:
Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2658-2662 (2017) - [c14]Jinnan Ding, Shuguo Li:
Determine the carry bit of carry-sum generated by unsigned MBE multiplier without final addition. FPL 2017: 1-4 - [c13]Jinnan Ding, Shuguo Li:
Broken-Karatsuba multiplication and its application to Montgomery modular multiplication. FPL 2017: 1-4 - [c12]Lijuan Li, Shuguo Li:
High throughput AES encryption/decryption with efficient reordering and merging techniques. FPL 2017: 1-4 - [c11]Yifeng Mo, Shuguo Li:
Fast RNS implementation of elliptic curve point multiplication in GF(p) with selected base pairs. FPL 2017: 1-6 - [c10]Yongcheng He, Shuguo Li:
A 3DES implementation especially for CBC feedback loop mode. ISCAS 2017: 1-4 - [c9]Lijuan Li, Shuguo Li:
Fast inversion in GF(2m) with polynomial basis using optimal addition chains. ISCAS 2017: 1-4 - [c8]Xufan Wu, Shuguo Li:
A new digital true random number generator based on delay chain feedback loop. ISCAS 2017: 1-4 - [c7]Jia Miao, Shuguo Li:
A design for high speed leading-zero counter. ISCE 2017: 22-23 - [c6]Xiang Feng, Shuguo Li:
Design of a fast number theoretical transform engine for fully homomorphic encryption. ISCE 2017: 86-87 - [c5]Xiang Feng, Shuguo Li:
A High-Speed and SPA-Resistant Implementation of ECC Point Multiplication Over GF(p). TrustCom/BigDataSE/ICESS 2017: 255-260 - [c4]Yifeng Mo, Shuguo Li:
Base Extent Optimization for RNS Montgomery Algorithm. TrustCom/BigDataSE/ICESS 2017: 1004-1009 - [c3]Jinnan Ding, Shuguo Li:
A Reconfigurable High-Speed ECC Processor Over NIST Primes. TrustCom/BigDataSE/ICESS 2017: 1064-1069 - 2016
- [j11]Yuanhao Wang, Shuguo Li:
A High-Speed Digital True Random Number Generator Based on Cross Ring Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(4): 806-818 (2016) - [j10]Xiaojing Du, Shuguo Li:
The ASIC Implementation of SM3 Hash Algorithm for High Throughput. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1481-1487 (2016) - [j9]Lijuan Li, Shuguo Li:
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1223-1232 (2016) - 2015
- [j8]Tao Wu, Shuguo Li, Litian Liu:
Fast RSA decryption through high-radix scalable Montgomery modular multipliers. Sci. China Inf. Sci. 58(6): 1-16 (2015) - [j7]Xiang Feng, Shuguo Li:
A High Performance FPGA Implementation of 256-bit Elliptic Curve Cryptography Processor Over GF(p). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(3): 863-869 (2015) - 2014
- [j6]Lijuan Li, Shuguo Li:
A Digital TRNG Based on Cross Feedback Ring Oscillators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 284-291 (2014) - 2013
- [j5]Tao Wu, Shuguo Li, Litian Liu:
Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications. Integr. 46(4): 323-332 (2013) - 2011
- [c2]Tao Wu, Shuguo Li, Litian Liu:
CSA-based design of feedforward scalable montgomery modular multiplier. ISSPIT 2011: 54-59 - 2010
- [j4]Shuguo Li, Fuqiang Cao:
Random numbers from an integrated CMOS double-scroll. IEICE Electron. Express 7(18): 1382-1387 (2010)
2000 – 2009
- 2009
- [j3]Shuguo Li, Jian Zhang:
Area-delay efficient parallel architecture for Fermat number transform. IEICE Electron. Express 6(8): 449-455 (2009) - [j2]Jian Zhang, Shuguo Li:
Data-recovery algorithm and circuit for cyclic convolution based on FNT. IEICE Electron. Express 6(14): 1019-1024 (2009) - [j1]Shuguo Li, Jian Zhang:
Efficient FPGA implementation of sharp FIR filters using the FRM technique. IEICE Electron. Express 6(23): 1656-1662 (2009) - [c1]Jian Zhang, Shuguo Li:
High Speed Parallel Architecture for Cyclic Convolution Based on FNT. ISVLSI 2009: 199-204
Coauthor Index
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