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Changze Liu
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2020 – today
- 2022
- [j3]Tinghuan Chen
, Qi Sun
, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu
:
Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 1990-2003 (2022) - 2021
- [c7]Tinghuan Chen
, Qi Sun
, Canhui Zhan, Changze Liu, Huatao Yu, Bei Yu:
Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks. ASP-DAC 2021: 898-903 - [c6]Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu:
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSCIRC 2021: 55-58 - [c5]Amita Rawat, Krishna K. Bhuwalka
, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu:
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks. ESSDERC 2021: 55-58
2010 – 2019
- 2018
- [j2]Shaofeng Guo, Runsheng Wang, Pengpeng Ren, Changze Liu, Mulong Luo, Xiaobo Jiang, Yangyuan Wang, Ru Huang:
Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits. Microelectron. Reliab. 81: 101-111 (2018) - [c4]Pengpeng Ren, Changze Liu, Sanping Wan, Jiayang Zhang, Zhuoqing Yu, Nie Liu, Yongsheng Sun, Runsheng Wang, Canhui Zhan, Zhenghao Gan, Waisum Wong, Yu Xia, Ru Huang:
New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology. IRPS 2018: 3-1 - 2015
- [c3]Changze Liu, Hyun-Chul Sagong, Hyejin Kim, Seungjin Choo, Hyunwoo Lee, Yoohwan Kim, Hyunjin Kim, Bisung Jo, Minjung Jin, Jinjoo Kim, Sangsu Ha, Sangwoo Pae, Jongwoo Park:
Systematical study of 14nm FinFET reliability: From device level stress to product HTOL. IRPS 2015: 2 - 2012
- [c2]Xin Huang, Tianwei Zhang, Runsheng Wang, Changze Liu, Yuchao Liu, Ru Huang:
Self-heating effects in gate-all-around silicon nanowire MOSFETs: Modeling and analysis. ISQED 2012: 727-731 - 2011
- [j1]Ru Huang, Runsheng Wang, Changze Liu, Liangliang Zhang
, Jing Zhuge, Yu Tao, Jinbin Zou, Yuchao Liu, Yangyuan Wang:
HCI and NBTI induced degradation in gate-all-around silicon nanowire transistors. Microelectron. Reliab. 51(9-11): 1515-1520 (2011) - [c1]Ru Huang, Runsheng Wang, Jing Zhuge, Changze Liu, Tao Yu, Liangliang Zhang, Xin Huang, Yujie Ai, Jinbin Zou, Yuchao Liu, Jiewen Fan, Huailin Liao, Yangyuan Wang:
Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling. CICC 2011: 1-8
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last updated on 2024-06-04 20:43 CEST by the dblp team
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