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Hai Huang 0010
Person information
- affiliation: University of Texas at Dallas, Texas Analog Center of Excellence, Richardson, TX, USA
Other persons with the same name
- Hai Huang — disambiguation page
- Hai Huang 0001 — Beijing University of Posts and Telecommunications, School of Information and Communication Engineering, China (and 1 more)
- Hai Huang 0002 — IBM T. J. Watson Research Center, Hawthorne, NY, USA (and 1 more)
- Hai Huang 0003 — Université Côte d'Azur, INRIA, Sophia Antipolis, France (and 3 more)
- Hai Huang 0004 — Harbin Engineering University, National Key Laboratory of Science and Technology on Underwater Vehicle, Harbin, China (and 1 more)
- Hai Huang 0005 — Shanghai Jiaotong University, Shanghai, China
- Hai Huang 0006 — Bundeswehr University Munich, Institute for Applied Computer Science, Germany (and 1 more)
- Hai Huang 0007 — Duke University, Durham, NC, USA
- Hai Huang 0008 — China Univ. of Mining & Technololgy, Xuzhou, China
- Hai Huang 0009 — Nanning Teachers College, Longzhou, China
- Hai Huang 0011 — Arizona State University, Department of Computer Science and Engineering, Tempe, AZ, USA (and 1 more)
- Hai Huang 0012 — University of Waterloo, Department of Electrical and Computer Engineering, Waterloo, Canada
- Hai Huang 0013 — Zhejiang University, Hangzhou, China
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2010 – 2019
- 2019
- [j3]Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu:
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. IEEE J. Solid State Circuits 54(2): 441-451 (2019) - 2017
- [j2]Hai Huang, Ling Du, Yun Chiu:
A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer. IEEE J. Solid State Circuits 52(6): 1551-1562 (2017) - [j1]Hai Huang, Hongda Xu, Brian Elies, Yun Chiu:
A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation. IEEE J. Solid State Circuits 52(12): 3235-3247 (2017) - [c2]Hai Huang, Sudipta Sarkar, Brian Elies, Yun Chiu:
28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation. ISSCC 2017: 472-473 - 2015
- [c1]Hai Huang, Ling Du, Yun Chiu:
A 1.2-GS/s 8-bit two-step SAR ADC in 65-nm CMOS with passive residue transfer. A-SSCC 2015: 1-4
Coauthor Index
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