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2020 – today
- 2025
[j90]Masanori Natsui, Takahiro Hanyu:
Design of an Intermittent-Computing-Oriented Nonvolatile Register With a Switching-Probability-Aware Store-and-Verify Scheme. IEEE Access 13: 38104-38114 (2025)- 2024
- [j89]Naoya Onizawa
, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu:
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access 12: 102050-102060 (2024) - [j88]Ken Asano, Masanori Natsui, Takahiro Hanyu:
Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware. IEICE Trans. Inf. Syst. 107(8): 958-965 (2024) - [c148]Fangcen Zhong, Masanori Natsui, Takahiro Hanyu:
Design of a High-Speed and Low-Power Threshold Adjustment Unit for Battery-Free Edge Devices. IJCNN 2024: 1-7 - [c147]Masanori Natsui, Ken Asano, Takahiro Hanyu:
Error-Tolerant Quantized Neural Network Based on Non-Weighted Arithmetic. ISMVL 2024: 42-46 - [c146]R. Kanda, Naoya Onizawa, Mathieu Léonardon, Vincent Gripon, Takahiro Hanyu:
Design Environment of Quantization-Aware Edge AI Hardware for Few-Shot Learning. MWSCAS 2024: 928-931 - [c145]Tomoo Yoshida, Masanori Natsui, Takahiro Hanyu:
Design of an Energy/Area-Aware MTJ-Based Nonvolatile Register with a Reference-Load Sharing Scheme. MWSCAS 2024: 1257-1261 - 2023
- [j87]Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu:
Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic. IEEE Access 11: 44923-44931 (2023) - [j86]Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 108-118 (2023) - [j85]Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu:
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. 34(12): 10999-11005 (2023) - [c144]Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Stochastic Implementation of Simulated Quantum Annealing on PYNQ. ICFPT 2023: 274-275 - [c143]Ken Asano, Masanori Natsui, Takahiro Hanyu:
Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network. ICECS 2023: 1-4 - [c142]Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Improving Stochastic Quantum-Like Annealing Based on Rerandomization. ICECS 2023: 1-4 - [c141]Fangcen Zhong, Masanori Natsui, Takahiro Hanyu:
High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control. ISCAS 2023: 1-5 - [c140]Ken Asano, Masanori Natsui, Takahiro Hanyu:
Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware. ISMVL 2023: 7-11 - [c139]Kaede Sakai, Masanori Natsui, Takahiro Hanyu:
Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing. MWSCAS 2023: 269-273 - [i4]Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu:
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR abs/2302.12454 (2023) - [i3]Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu:
Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing. CoRR abs/2304.11839 (2023) - 2022
- [j84]Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN. FLAP 9(3): 653-674 (2022) - [c138]Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing. ICECS 2022 2022: 1-4 - [c137]Daisuke Suzuki, Takahiro Hanyu:
A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator. MCSoC 2022: 53-60 - [c136]Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu:
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator. MWSCAS 2022: 1-4 - 2021
- [j83]Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu:
Sparse Random Signals for Fast Convergence on Invertible Logic. IEEE Access 9: 62890-62898 (2021) - [j82]Daisuke Suzuki, Takahiro Hanyu:
Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow. IEICE Trans. Inf. Syst. 104-D(8): 1111-1120 (2021) - [j81]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56(4): 1116-1128 (2021) - [j80]Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu:
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices. IEEE Open J. Circuits Syst. 2: 782-791 (2021) - [j79]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 655-665 (2021) - [j78]Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu:
Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 67-76 (2021) - [c135]Naoya Onizawa, Takahiro Hanyu:
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. ISCAS 2021: 1-5 - [c134]Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu:
A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting. MCSoC 2021: 92-97 - [c133]Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu:
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices. SiPS 2021: 1-6 - 2020
- [j77]Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access 8: 188004-188014 (2020) - [j76]Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu:
Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic. FLAP 7(1): 41-58 (2020) - [j75]Naoya Onizawa, Ren Arakawa, Takahiro Hanyu:
Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory. FLAP 7(1): 89-109 (2020) - [j74]Makoto Kato, Naoya Onizawa, Takahiro Hanyu:
Design Automation of Invertible Logic Circuit from a Standard HDL Description. FLAP 8(5): 1311-1333 (2020) - [j73]Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu:
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1541-1550 (2020) - [j72]Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2171-2181 (2020) - [j71]Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu:
Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2370-2382 (2020) - [c132]Daisuke Suzuki, Takahiro Hanyu:
Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA. ISMVL 2020: 194-199 - [c131]Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices. NEWCAS 2020: 283-286 - [c130]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j70]Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54(11): 2991-3004 (2019) - [j69]Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu:
Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices. Microelectron. J. 83: 39-49 (2019) - [j68]Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu:
Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2263-2274 (2019) - [c129]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. ACSSC 2019: 312-316 - [c128]Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu:
FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic. ICECS 2019: 115-116 - [c127]Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu:
Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN. ICECS 2019: 117-118 - [c126]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge. ICECS 2019: 434-437 - [c125]Tomoki Chiba, Masanori Natsui, Takahiro Hanyu:
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks. ISMVL 2019: 91-96 - [c124]Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC 2019: 202-204 - 2018
- [j67]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 444-453 (2018) - [j66]Masanori Natsui, Tomoki Chiba, Takahiro Hanyu:
Design of MTJ-Based nonvolatile logic gates for quantized neural networks. Microelectron. J. 82: 13-21 (2018) - [j65]Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82: 46-61 (2018) - [j64]Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu:
Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2696-2708 (2018) - [j63]Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross:
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. J. Signal Process. Syst. 90(5): 709-725 (2018) - [c123]Daisuke Suzuki, Takahiro Hanyu:
Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only). FPGA 2018: 291 - [c122]Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Study of Stochastic Invertible Multiplier Designs. ICECS 2018: 649-650 - [c121]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure. ISCAS 2018: 1-5 - [c120]Hiroki Suda, Masanori Natsui, Takahiro Hanyu:
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. ISMVL 2018: 56-61 - [c119]Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu:
Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter. ISMVL 2018: 156-161 - 2017
- [j62]Takahiro Hanyu:
Foreword. IEICE Trans. Inf. Syst. 100-D(8): 1555 (2017) - [j61]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation. IEICE Trans. Inf. Syst. 100-D(8): 1592-1602 (2017) - [j60]Daisuke Suzuki, Takahiro Hanyu:
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. IEICE Trans. Inf. Syst. 100-D(8): 1618-1624 (2017) - [j59]Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Emerg. Top. Comput. 5(2): 151-163 (2017) - [j58]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2688-2699 (2017) - [j57]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu:
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2724-2735 (2017) - [c118]Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda:
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC 2017: 118-125 - [c117]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui:
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE 2017: 548-553 - [c116]Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability. ESSCIRC 2017: 43-46 - [c115]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu:
Design of stochastic asymmetric compensation filters for auditory signal processing. GlobalSIP 2017: 1315-1319 - [c114]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu:
Evaluation of Stochastic Cascaded IIR Filters. ISMVL 2017: 224-229 - [c113]Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu:
NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS 2017: 309-312 - 2016
- [j56]Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross:
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 13-24 (2016) - [j55]Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno:
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 109-119 (2016) - [j54]Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory. J. Multiple Valued Log. Soft Comput. 26(1-2): 125-140 (2016) - [j53]Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno:
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104(10): 1844-1863 (2016) - [c112]Daisuke Suzuki, Takahiro Hanyu:
A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. FPL 2016: 1-4 - [c111]Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu:
Gammatone filter based on stochastic computation. ICASSP 2016: 1036-1040 - [c110]Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS 2016: 1878-1881 - [c109]Daisuke Suzuki, Takahiro Hanyu:
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme. ISMVL 2016: 5-10 - [c108]Naoto Sugaya, Masanori Natsui, Takahiro Hanyu:
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. ISMVL 2016: 72-77 - [c107]Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata:
Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation. ISMVL 2016: 223-228 - [c106]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI implementation of deep neural networks using integral stochastic computing. ISTC 2016: 216-220 - [c105]Masanori Natsui, Naoto Sugaya, Takahiro Hanyu:
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning. NEWCAS 2016: 1-4 - [c104]Naoya Onizawa, Takahiro Hanyu:
Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations. NEWCAS 2016: 1-4 - 2015
- [j52]Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50(2): 476-489 (2015) - [j51]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Gabor Filter Based on Stochastic Computation. IEEE Signal Process. Lett. 22(9): 1224-1228 (2015) - [c103]Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki:
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE 2015: 1006-1011 - [c102]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu:
Frequency-flexible stochastic Gabor filter. DSP 2015: 458-462 - [c101]Akira Mochizuki, Naoto Yube, Takahiro Hanyu:
Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor. IECON 2015: 3283-3288 - [c100]Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu:
Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors. ISMVL 2015: 109-114 - [c99]Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu:
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. ISMVL 2015: 152-157 - [c98]Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu:
Scaled IIR filter based on stochastic computation. MWSCAS 2015: 1-4 - [c97]Daisuke Suzuki, Takahiro Hanyu:
Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure. MWSCAS 2015: 1-4 - [c96]Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. NANOARCH 2015: 39-44 - [c95]Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu:
Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop. NEWCAS 2015: 1-4 - [c94]Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross:
Stochastic implementation of the disparity energy model for depth perception. SiPS 2015: 1-6 - [c93]Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC 2015: 172- - [i2]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. CoRR abs/1509.08972 (2015) - 2014
- [j50]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross:
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 460-474 (2014) - [j49]Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express 11(3): 20131006 (2014) - [j48]Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11(10): 20140297 (2014) - [j47]Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11(13): 20140296 (2014) - [j46]Naoya Onizawa, Takahiro Hanyu:
Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element. IEICE Electron. Express 11(24): 20141017 (2014) - [j45]Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. 97-D(6): 1546-1556 (2014) - [j44]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model. IEICE Trans. Inf. Syst. 97-D(9): 2286-2295 (2014) - [j43]Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu:
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. IEICE Trans. Inf. Syst. 97-D(9): 2304-2311 (2014) - [j42]Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu:
High-Throughput Compact Delay-Insensitive Asynchronous NoC Router. IEEE Trans. Computers 63(3): 637-649 (2014) - [j41]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu:
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 865-876 (2014) - [j40]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. J. Signal Process. Syst. 76(2): 185-194 (2014) - [c92]Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura:
An NoC-based evaluation platform for safety-critical automotive applications. APCCAS 2014: 679-682 - [c91]Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu:
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. APCCAS 2014: 683-686 - [c90]Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu:
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. ASYNC 2014: 1-8 - [c89]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi:
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS 2014: 1588-1591 - [c88]Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu:
Energy-aware current-mode inter-chip link for a dependable GALS NoC platform. ISCAS 2014: 1865-1868 - [c87]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link. ISMVL 2014: 67-72 - [c86]Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. ISMVL 2014: 208-213 - [c85]Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu:
Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL 2014: 220-225 - [c84]Masanori Natsui, Takahiro Hanyu:
Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors. ISMVL 2014: 243-247 - [c83]Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi:
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC 2014: 184-185 - [c82]Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu:
Analog-to-stochastic converter using magnetic-tunnel junction devices. NANOARCH 2014: 59-64 - [c81]Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu:
Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM. NEWCAS 2014: 193-196 - [c80]Masanori Natsui, Takahiro Hanyu:
Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI. NEWCAS 2014: 468 - [c79]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross:
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. SiPS 2014: 133-138 - [i1]Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. CoRR abs/1402.0808 (2014) - 2013
- [j39]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu:
High-throughput CAM based on a synchronous overlapped search scheme. IEICE Electron. Express 10(7): 20130148 (2013) - [j38]Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10(23): 20130772 (2013) - [j37]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links. IEICE Trans. Inf. Syst. 96-D(9): 1952-1961 (2013) - [j36]Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits 48(6): 1511-1520 (2013) - [j35]Masanori Natsui, Takahiro Hanyu:
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices. J. Multiple Valued Log. Soft Comput. 21(5-6): 597-608 (2013) - [c78]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems. ASYNC 2013: 8-15 - [c77]Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi:
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS 2013: 105-109 - [c76]Takahiro Hanyu:
Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor. ISCAS 2013: 117-120 - [c75]Masanori Natsui, Kiyohiro Kashiuchi, Takahiro Hanyu:
Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications. ISMVL 2013: 146-151 - [c74]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating. ISMVL 2013: 254-259 - [c73]Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto:
Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information. ISMVL 2013: 266-271 - [c72]Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC 2013: 194-195 - 2012
- [j34]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(6): 1018-1029 (2012) - [j33]Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu:
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique. J. Multiple Valued Log. Soft Comput. 19(1-3): 219-231 (2012) - [c71]Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC 2012: 475-476 - [c70]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu:
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. ASYNC 2012: 41-48 - [c69]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974 - [c68]Youngkeun Kim, Masanori Natsui, Takahiro Hanyu:
Variation-resilient current-mode logic circuit design using MTJ devices. ISCAS 2012: 2705-2708 - [c67]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links. ISMVL 2012: 13-18 - [c66]Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross:
Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes. ISMVL 2012: 92-97 - [c65]Shoun Matsunaga, Takahiro Hanyu:
Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM. ISMVL 2012: 98-103 - [c64]Masanori Natsui, Takaaki Nagashima, Takahiro Hanyu:
Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control. ISMVL 2012: 214-219 - [c63]Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki:
Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs. ISVLSI 2012: 302-307 - [c62]Daisuke Suzuki, Masanori Natsui, Takahiro Hanyu:
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA. MWSCAS 2012: 334-337 - [c61]Masanori Natsui, Takahiro Hanyu:
Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system. NEWCAS 2012: 97-100 - [c60]Magdalena Sihotang, Shoun Matsunaga, Takahiro Hanyu:
Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction. NEWCAS 2012: 485-488 - [c59]Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Multi-chip NoCs for Automotive Applications. PRDC 2012: 105-110 - [c58]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Clockless Stochastic Decoding of Low-Density Parity-Check Codes. SiPS 2012: 143-148 - [c57]Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. VLSIC 2012: 44-45 - [c56]Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC 2012: 46-47 - 2011
- [j32]Satoru Hanzawa, Takahiro Hanyu:
Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device. IEICE Trans. Electron. 94-C(8): 1302-1310 (2011) - [j31]Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu:
Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(8): 1933-1943 (2011) - [c55]Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring. DATE 2011: 776-781 - [c54]Takahiro Hanyu:
Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry. ACM Great Lakes Symposium on VLSI 2011: 437-438 - [c53]Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu:
Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system. ISCAS 2011: 2067-2070 - [c52]Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu:
Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme. ISMVL 2011: 99-104 - [c51]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links. ISMVL 2011: 236-241 - 2010
- [j30]Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. IEICE Trans. Electron. 93-C(5): 602-607 (2010) - [j29]Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. IEICE Trans. Electron. 93-C(5): 608-613 (2010) - [j28]Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu:
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. IEICE Trans. Inf. Syst. 93-D(8): 2080-2088 (2010) - [j27]Naoya Onizawa, Takahiro Hanyu:
Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link. IEICE Trans. Inf. Syst. 93-D(8): 2089-2099 (2010) - [j26]Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet:
Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 482-489 (2010) - [c50]Naoya Onizawa, Takahiro Hanyu:
High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. ISCAS 2010: 157-160 - [c49]Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu:
One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control. ISMVL 2010: 211-216 - [c48]Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu:
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. ISMVL 2010: 235-240 - [c47]Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu:
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI (Selected papers) 2010: 17-30 - [c46]Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu:
Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. ISVLSI 2010: 357-362 - [c45]Takahiro Hanyu:
Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact. VTS 2010: 258
2000 – 2009
- 2009
- [j25]Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet:
High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving. IEICE Trans. Electron. 92-C(6): 867-874 (2009) - [c44]Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE 2009: 433-435 - [c43]Yo Ohtake, Naoya Onizawa, Takahiro Hanyu:
High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme. ISCAS 2009: 1000-1003 - [c42]Naoya Onizawa, Takahiro Hanyu:
Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. ISMVL 2009: 36-41 - [c41]Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu:
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ISMVL 2009: 60-65 - 2008
- [j24]Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu:
Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling. IEICE Trans. Electron. 91-C(4): 581-588 (2008) - [j23]Masatomo Miura, Takahiro Hanyu:
Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation. IEICE Trans. Electron. 91-C(4): 589-594 (2008) - [c40]Hirokatsu Shirahama, Takahiro Hanyu:
Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. ISMVL 2008: 8-13 - [c39]Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu:
Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices. ISMVL 2008: 14-19 - [c38]Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu:
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit. ISMVL 2008: 70-75 - 2007
- [j22]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Trans. Electron. 90-C(4): 683-691 (2007) - [c37]Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu:
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. ASP-DAC 2007: 116-117 - [c36]Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto:
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43 - [c35]Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu:
Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme. ISMVL 2007: 44 - [c34]Akira Mochizuki, Masatomo Miura, Takahiro Hanyu:
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ISMVL 2007: 57 - 2006
- [j21]Takahiro Hanyu:
Special Section on Novel Device Architectures and System Integration Technologies. IEICE Trans. Electron. 89-C(11): 1491 (2006) - [j20]Naoya Onizawa, Takahiro Hanyu:
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic. IEICE Trans. Electron. 89-C(11): 1575-1580 (2006) - [j19]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Trans. Electron. 89-C(11): 1591-1597 (2006) - [j18]Tomohiro Takahashi, Takahiro Hanyu:
Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing. IEICE Trans. Electron. 89-C(11): 1598-1604 (2006) - [c33]Akira Mochizuki, Takahiro Hanyu:
Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ISMVL 2006: 5 - [c32]Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL 2006: 14 - 2005
- [j17]Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu:
TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(6): 1408-1415 (2005) - [j16]Michitaka Kameyama, Takahiro Hanyu, Takafumi Aoki:
Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 407-436 (2005) - [j15]Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama:
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 481-497 (2005) - [j14]Tomohiro Takahashi, Takahiro Hanyu:
Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits. J. Multiple Valued Log. Soft Comput. 11(5-6): 499-517 (2005) - [j13]Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama:
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 619-632 (2005) - [c31]Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu:
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL 2005: 138-143 - 2004
- [j12]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu:
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI. IEEE J. Solid State Circuits 39(6): 919-926 (2004) - [c30]Tomohiro Takahashi, Takahiro Hanyu:
Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication. ISMVL 2004: 20-25 - [c29]Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu:
Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ISMVL 2004: 192-197 - [c28]Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu:
A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices. ISMVL 2004: 340-345 - 2003
- [j11]Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama:
Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization. J. Multiple Valued Log. Soft Comput. 9(1): 5-21 (2003) - [j10]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama:
Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications. J. Multiple Valued Log. Soft Comput. 9(1): 23-42 (2003) - [c27]Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama:
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic. ISMVL 2003: 99-104 - [c26]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Dynamic Source-Coupled Logic. ISMVL 2003: 207-212 - 2002
- [c25]Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama:
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition. ISMVL 2002: 161-167 - [c24]Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama:
Fully Source-Coupled Logic Based Multiple-Valued VLSI. ISMVL 2002: 270-275 - 2001
- [c23]Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama:
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources. ISMVL 2001: 21-26 - [c22]Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran:
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits. ISMVL 2001: 167-172 - [c21]Takahiro Hanyu:
Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI. ISMVL 2001: 241-246 - 2000
- [c20]Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama:
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels. ISMVL 2000: 382-390 - [c19]Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama:
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage. ISMVL 2000: 423-429 - [c18]Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama:
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438-446 - [c17]Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama:
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic. PRDC 2000: 27-36
1990 – 1999
- 1999
- [c16]Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama:
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs. ISMVL 1999: 30-35 - [c15]Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama:
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1999: 275-279 - 1998
- [j9]Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama:
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application. Syst. Comput. Jpn. 29(11): 40-47 (1998) - [j8]Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama:
Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Syst. Comput. Jpn. 29(11): 48-54 (1998) - [c14]Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama:
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic. ISMVL 1998: 134-139 - [c13]Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama:
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL 1998: 270-275 - 1997
- [c12]Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama:
Low-power multiple-valued current-mode integrated circuit with current-source control and its application. ASP-DAC 1997: 413-418 - [c11]Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama:
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1997: 175-182 - 1996
- [j7]Takahiro Hanyu, N. Kanagawa, Michitaka Kameyama:
Design of a one-transistor-cell multiple-valued CAM. IEEE J. Solid State Circuits 31(11): 1669-1674 (1996) - [j6]Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama:
Design of a one-transistor-cell multiple-valued CAM. IEEE J. Solid State Circuits 31(11): 1669-1674 (1996) - [c10]Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu:
A Multiple-Valued Ferroelectric Content-Addressable Memory. ISMVL 1996: 74-79 - [c9]Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama:
Quaternary Universal-Literal CAM for Cellular Logic Image Processing. ISMVL 1996: 224-229 - 1995
- [j5]Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama:
Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate. IEICE Trans. Inf. Syst. 78-D(8): 951-958 (1995) - [j4]Takahiro Hanyu, Michitaka Kameyama:
A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic. IEEE J. Solid State Circuits 30(11): 1239-1245 (1995) - [c8]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL 1995: 64-71 - [c7]Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama:
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems. ISMVL 1995: 92-97 - 1994
- [c6]Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama:
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL 1994: 19-26 - 1993
- [c5]Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi:
A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. ISMVL 1993: 170-175 - 1992
- [c4]Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi:
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. ISMVL 1992: 274-281 - 1991
- [c3]Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi:
A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. ISMVL 1991: 16-23 - [c2]Takahiro Hanyu, Tatsuo Higuchi:
A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. ISMVL 1991: 24-31 - 1990
- [c1]Takahiro Hanyu, Tatsuo Higuchi:
Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. ISMVL 1990: 18-23
1980 – 1989
- 1989
- [j3]Takahiro Hanyu, Tatsuo Higuchi:
High-density quaternary logic array chip for knowledge information processing systems. IEEE J. Solid State Circuits 24(4): 916-921 (1989) - [j2]Takahiro Hanyu, Tatsuo Higuchi:
Design of a Multiple-Valued Associative Memory. Syst. Comput. Jpn. 20(12): 23-33 (1989) - 1987
- [j1]Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi:
Design and implementation of an nmos image processor based on quaternary logic. Syst. Comput. Jpn. 18(3): 92-106 (1987)
Coauthor Index
Hiroaki Honjo
aka: Hiroaki Honjou
aka: Hiroaki Honjou
[j89] [c146] [j87] [j86] [j85] [c144] [c142] [i4] [i3] [j84] [c138] [j83] [j80] [j79] [j78] [c135] [c133] [j77] [j76] [j75] [j74] [j73] [j72] [j71] [c131] [j68] [c129] [c128] [c127] [c126] [j67] [j65] [j64] [j63] [c122] [c121] [c119] [j61] [j59] [j58] [j57] [c118] [c117] [c116] [c115] [c114] [c113] [j56] [j54] [j53] [c111] [c107] [c106] [c104] [j51] [c103] [c102] [c100] [c98] [c96] [c95] [c94] [i2] [j50] [j46] [j45] [j44] [j42] [j41] [j40] [c91] [c90] [c86] [c85] [c82] [c81] [c79] [i1] [j39] [j37] [c78] [c74] [j34] [c70] [c67] [c66] [c59] [c58] [j31] [c55] [c53] [c51] [j27] [j26] [c50] [c49] [c47] [c46] [j25] [c43] [c42] [j24] [c38] [j20] [c31]
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