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ORCIDHirokatsu Shirahama
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2010 – 2019
- 2014
[j5]Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu:
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. 97-D(6): 1546-1556 (2014)- [j4]Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu:
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. IEICE Trans. Inf. Syst. 97-D(9): 2304-2311 (2014) - [c7]Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu:
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. APCCAS 2014: 683-686 - [c6]Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu:
Energy-aware current-mode inter-chip link for a dependable GALS NoC platform. ISCAS 2014: 1865-1868 - [c5]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link. ISMVL 2014: 67-72 - 2010
- [j3]Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui
, Takahiro Hanyu:
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. IEICE Trans. Inf. Syst. 93-D(8): 2080-2088 (2010)
2000 – 2009
- 2009
- [c4]Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu:
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ISMVL 2009: 60-65 - 2008
- [c3]Hirokatsu Shirahama, Takahiro Hanyu:
Design of High-Performance Quaternary Adders Based on Output-Generator Sharing. ISMVL 2008: 8-13 - 2007
- [j2]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Trans. Electron. 90-C(4): 683-691 (2007) - [c2]Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto:
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43 - 2006
- [j1]Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Trans. Electron. 89-C(11): 1591-1597 (2006) - [c1]Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu:
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL 2006: 14
Coauthor Index
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