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ORCIDRakefet Kol
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2000 – 2009
- 2004
[c7]Alex Branover, Rakefet Kol, Ran Ginosar:
Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones. DATE 2004: 870-877- 2001
- [j1]Kenneth S. Stevens, Shai Rotem, Ran Ginosar, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun, Rakefet Kol, Charles Dike, Marly Roncken:
An asynchronous instruction length decoder. IEEE J. Solid State Circuits 36(2): 217-228 (2001)
1990 – 1999
- 1999
- [c6]Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers
, Kenneth Y. Yun:
RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70 - 1998
- [c5]Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun:
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80- - [c4]Ran Ginosar, Rakefet Kol:
Adaptive synchronization. ICCD 1998: 188-189 - [c3]Rakefet Kol, Ran Ginosar:
Kin: A High Performance Asynchronous Processor Architecture. International Conference on Supercomputing 1998: 433-440 - 1997
- [c2]Rakefet Kol, Ran Ginosar:
A Double-Latched Asynchronous Pipeline. ICCD 1997: 706-712 - 1996
- [c1]Rakefet Kol, Ran Ginosar, Goel Samuel:
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. ASYNC 1996: 164-174
Coauthor Index
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