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2020 – today
- 2024
[c8]Jesko Flemming
, Bernhard Wicht, Pascal Witte:
A DAC Sharing and Linearization Technique for Time-Interleaved Incremental Delta-Sigma ADCs. ISCAS 2024: 1-5- 2023
- [c7]Jesko Flemming, Bernhard Wicht, Pascal Witte:
A Noise-Canceling SMASH Architecture for Discrete-Time Bandpass Delta-Sigma ADCs. ISCAS 2023: 1-5 - [c6]Jesko Flemming, Bernhard Wicht, Pascal Witte:
Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC Architectures. SMACD 2023: 1-4
2010 – 2019
- 2014
- [j4]John G. Kauffman, Pascal Witte, Matthias Lehmann, Joachim Becker, Yiannos Manoli, Maurits Ortmanns:
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW. IEEE J. Solid State Circuits 49(2): 392-404 (2014) - 2012
- [c5]Pascal Witte, John G. Kauffman, Timon Brückner, Joachim Becker, Maurits Ortmanns:
An error estimation technique for lowpass and bandpass ΣΔ ADC feedback DACs using a residual test signal. ISCAS 2012: 73-76 - [c4]Pascal Witte, John G. Kauffman, Joachim Becker, Yiannos Manoli, Maurits Ortmanns:
A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW. ISSCC 2012: 154-156 - 2011
- [j3]John G. Kauffman, Pascal Witte, Joachim Becker, Maurits Ortmanns:
An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR. IEEE J. Solid State Circuits 46(12): 2869-2881 (2011) - [j2]Pascal Witte, John G. Kauffman, Joachim Becker, Maurits Ortmanns:
A Correlation-Based Background Error Estimation Technique for Bandpass Delta-Sigma ADC DACs. IEEE Trans. Circuits Syst. II Express Briefs 58-II(11): 748-752 (2011) - [c3]John G. Kauffman, Pascal Witte, Joachim Becker, Maurits Ortmanns:
An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization. ISSCC 2011: 472-474 - 2010
- [j1]Pascal Witte, Maurits Ortmanns:
Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1500-1512 (2010) - [c2]Pascal Witte, Carsten Noeske, Maurits Ortmanns:
Hardware complexity of a correlation based background DAC error estimation technique for sigma-delta ADCs. ISCAS 2010: 2167-2170
2000 – 2009
- 2009
- [c1]Pascal Witte, Maurits Ortmanns:
A Background DAC Error Estimation in Sigma-Delta ADCs using a Pseudo Random Noise based Correlation Technique. ISCAS 2009: 1549-1552
Coauthor Index
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