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ORCIDPaulo F. Butzen
Paulo Francisco Butzen
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2020 – today
- 2024
[c49]Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
Extending Multilevel ALS to Design ATMRs. LASCAS 2024: 1-5- [c48]Clayton R. Farias, Tiago R. Balen, Paulo F. Butzen:
Cross-Section Estimation for Assessment of Circuit Susceptibility to Radiation. LATS 2024: 1-6 - [c47]Glória D. Claro da Silva, Rafael B. Schvittz, Paulo F. Butzen:
Transistor-Level Logic Gates Ranking Strategy for Selective Hardening. SBESC 2024: 1-6 - 2023
- [j14]Tiago R. Balen
, Carlos J. González, Ingrid F. V. Oliveira, Leomar S. da Rosa Jr., Rafael Iankowski Soares, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen:
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems. J. Electron. Test. 39(4): 409-420 (2023) - [c46]Renato D. Peralta, Joao P. Nespolo, Paulo F. Butzen, Mariana Kolberg, André Inácio Reis:
An Improved method to join BDDs for incompletely specified Boolean functions. ISCAS 2023: 1-5 - [c45]Gabriel Ammes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis. ISVLSI 2023: 1-6 - [c44]Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
ATMR design by construction based on two-level ALS. SBCCI 2023: 1-6 - [c43]Cleiton Magano Marques, Leonardo Heitich Brendler, Frédéric Wrobel, Alexandra L. Zimpeck, Walter E. Calienes Bartra, Paulo F. Butzen, Cristina Meinhardt:
A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures. SBCCI 2023: 1-6 - [c42]Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis:
Effect of Unique Table Implementation in the Performance of BDD Packages. SBCCI 2023: 1-6 - 2022
- [j13]Cesar de S. Dias, Felipe S. Marranghello, Raphael Martins Brum, Paulo F. Butzen:
A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(4): 878-887 (2022) - [j12]Augusto Andre Souza Berndt, Cristina Meinhardt, André Inácio Reis, Paulo F. Butzen:
Optimizing machine learning logic circuits with constant signal propagation. Integr. 87: 293-305 (2022) - [j11]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5126-5130 (2022) - [c41]Ingrid F. V. Oliveira, Matheus F. Pontes, Rafael B. Schvittz, Leomar S. da Rosa Jr., Paulo F. Butzen, Rafael Iankowski Soares:
Fault Tolerance Evaluation of Different Majority Voter Designs. ISCAS 2022: 185-189 - [c40]Matheus F. Pontes, Ingrid F. V. Oliveira, Rafael B. Schvittz, Leomar Soares da Rosa Jr., Paulo F. Butzen:
The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis. ISCAS 2022: 1610-1614 - [c39]Eduarde D. Brandão, Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis:
Possible Reductions to Generate circuits from BDDs. ISVLSI 2022: 406-409 - [c38]Guilherme B. Manske, Clayton R. Farias, Paulo F. Butzen, Leomar S. da Rosa:
A Fast Approximate Function Generation Method to ATMR Architecture. LASCAS 2022: 1-4 - [c37]Clayton R. Farias, Rafael B. Schvittz, Tiago R. Balen, Paulo F. Butzen:
Evaluating Soft Error Reliability of Combinational Circuits Using a Monte Carlo Based Method. LATS 2022: 1-6 - 2021
- [j10]Cleiton Magano Marques, Cristina Meinhardt, Paulo Francisco Butzen:
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions. J. Electron. Test. 37(2): 263-270 (2021) - [c36]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c35]Maria Eduarda de Melo Hang, Cleiton Magano Marques, Paulo F. Butzen, Cristina Meinhardt:
Soft Error Sensibility Window at FinFET DICE SRAM. LASCAS 2021: 1-4 - [c34]Isadora Oliveira, Marcelo Danigno, Paulo F. Butzen, Ricardo Reis:
Benchmarking Open Access VLSI Partitioning Tools. LASCAS 2021: 1-4 - [c33]Tiago R. Balen, Carlos J. González, Ingrid F. V. Oliveira, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. de Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen:
Reliability Evaluation of Voters for Fault Tolerant Approximate Systems. LATS 2021: 1-6 - [i2]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. CoRR abs/2112.00621 (2021) - 2020
- [c32]Mateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Paulo F. Butzen, Ricardo Reis:
Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited Paper. ICCAD 2020: 113:1-113:8 - [c31]Rafael B. Schvittz, Paulo F. Butzen, Leomar S. da Rosa:
Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients. ITC 2020: 1-9 - [c30]Cleiton Magano Marques, Cristina Meinhardt, Paulo F. Butzen:
Soft Error Reliability of SRAM cells during the three operation states. LATS 2020: 1-6 - [i1]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [c29]Jorge Ferreira, Paulo F. Butzen, Cristina Meinhardt, Ricardo A. L. Reis:
FBM: A Simple and Fast Algorithm for Placement Legalization. ICECS 2019: 209-212 - [c28]Marcelo Danigno, Paulo F. Butzen, Jorge Ferreira, André Oliveira, Eder Monteiro, Mateus Fogaça, Ricardo Augusto da Luz Reis:
Proposal and Evaluation of Pin Access Algorithms for Detailed Routing. ICECS 2019: 602-605 - [c27]Augusto Andre Souza Berndt, Alan Mishchenko, Paulo Francisco Butzen, André Inácio Reis:
Reduction of neural network circuits by constant and nearly constant signal propagation. SBCCI 2019: 29 - [c26]Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa, Paulo F. Butzen:
An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults. VLSI-SoC (Selected Papers) 2019: 69-88 - [c25]Rafael B. Schvittz, Denis Teixeira Franco, Leomar Soares, Paulo Francisco Butzen:
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates. VLSI-SoC 2019: 185-190 - [c24]Rafael B. Schvittz, Leomar Soares, Paulo Francisco Butzen:
Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability Estimation. VLSI-SoC 2019: 234-235 - 2018
- [j9]Roberto B. Almeida, Cleiton Magano Marques, Paulo F. Butzen, Fábio G. R. G. da Silva, Ricardo A. L. Reis, Cristina Meinhardt:
Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies. Microelectron. Reliab. 88-90: 196-202 (2018) - [c23]Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen:
Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults. ICECS 2018: 357-360 - [c22]Matheus F. Pontes, Paulo F. Butzen, Rafael B. Schvittz, Leomar S. da Rosa Jr., Denis Teixeira Franco:
The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. ICECS 2018: 433-436 - [c21]Rafael B. Schvittz, Matheus F. Pontes, Cristina Meinhardt, Denis Teixeira Franco, Lirida A. B. Naviner, Leomar S. da Rosa, Paulo F. Butzen:
Reliability evaluation of circuits designed in multi- and single-stage versions. LASCAS 2018: 1-4 - [c20]Ingrid F. V. Oliveira, Rafael B. Schvittz, Paulo F. Butzen:
Fault masking ratio analysis of majority voters topologies. LATS 2018: 1-6 - [c19]Roberto B. Almeida, Paulo F. Butzen, Cristina Meinhardt:
16NM 6T and 8T CMOS SRAM Cell Robustness Against Process Variability and Aging Effects. SBCCI 2018: 1-6 - [c18]Cesar de S. Dias, Paulo F. Butzen:
A Novel SPICE Model of Memristive Devices with Threshold Current Based Control. SBCCI 2018: 1-6 - 2017
- [c17]Gabriel S. Porto, Paulo F. Butzen, Denis Teixeira Franco:
Exploring BDDs to reduce test pattern set. LATS 2017: 1-4 - 2016
- [j8]Mariem Slimani, Paulo F. Butzen, Lirida A. B. Naviner, You Wang, Hao Cai:
Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters. Microelectron. Reliab. 64: 48-53 (2016) - [c16]Fábio G. R. G. da Silva, Paulo F. Butzen, Cristina Meinhardt:
PVT variability analysis of FinFET and CMOS XOR circuits at 16nm. ICECS 2016: 528-531 - [c15]Rafael B. Schivittz, Denis Teixeira Franco, Cristina Meinhardt, Paulo F. Butzen:
A probabilistic model for stuck-on faults in combinational logic gates. LATS 2016: 39-44 - [c14]Eduardo Liebl, Cristina Meinhardt, Paulo F. Butzen:
Reliability analysis of majority voters under permanent faults. LATS 2016: 180 - [c13]Rafael B. Schivittz, Rafael Fritz, Denis Teixeira Franco, Lirida A. B. Naviner, Cristina Meinhardt, Paulo F. Butzen:
Inserting permanent fault input dependence on PTM to improve robustness evaluation. SBCCI 2016: 1-6 - 2015
- [c12]Helder H. Avelar, Paulo F. Butzen, Renato P. Ribas:
Automatic circuit generation for sequential logic debug. ICECS 2015: 141-144 - [c11]Rafael B. Schivittz, Cristina Meinhardt, Paulo F. Butzen:
An evaluation of BTI degradation of 32nm standard cells. ICECS 2015: 661-664 - [c10]Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
An Incremental Timing-Driven flow using quadratic formulation for detailed placement. VLSI-SoC 2015: 1-6 - 2013
- [j7]Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
BTI, HCI and TDDB aging impact in flip-flops. Microelectron. Reliab. 53(9-11): 1355-1359 (2013) - [j6]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
BTI and HCI first-order aging estimation for early use in standard cell technology mapping. Microelectron. Reliab. 53(9-11): 1360-1364 (2013) - [c9]Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
A methodology to evaluate the aging impact on flip-flops performance. SBCCI 2013: 1-6 - 2012
- [j5]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectron. Reliab. 52(9-10): 1822-1826 (2012) - 2011
- [j4]John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 787-795 (2011) - [c8]Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD 2011: 279-284 - [c7]Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI 2011: 103-108 - 2010
- [j3]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. J. Low Power Electron. 6(1): 192-200 (2010) - [j2]Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas:
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. Microelectron. J. 41(4): 247-255 (2010) - [j1]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Transistor network restructuring against NBTI degradation. Microelectron. Reliab. 50(9-11): 1298-1303 (2010)
2000 – 2009
- 2009
- [c6]Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
Routing Resistance Influence in Loading Effect on Leakage Analysis. PATMOS 2009: 317-325 - 2008
- [c5]John Keane, Shrinivas Venkatraman, Paulo F. Butzen, Chris H. Kim:
An array-based test circuit for fully automated gate dielectric breakdown characterization. CICC 2008: 121-124 - [c4]Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas:
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ACM Great Lakes Symposium on VLSI 2008: 407-410 - 2007
- [c3]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI 2007: 269-274 - [c2]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI 2007: 512-513 - [c1]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS 2007: 474-484
Coauthor Index
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