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ORCIDGuilherme Flach
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2010 – 2019
- 2017
[c19]Guilherme Flach, Mateus Fogaça
, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Rsyn: An Extensible Physical Synthesis Framework. ISPD 2017: 33-40- 2016
- [c18]Mateus Fogaça, Guilherme Flach, Jucemar Monteiro, Marcelo O. Johann, Ricardo Reis:
Quadratic timing objectives for incremental timing-driven placement optimization. ICECS 2016: 620-623 - [c17]Guilherme Flach, Mateus Fogaça, Jucemar Monteiro, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Drive Strength Aware Cell Movement Techniques for Timing Driven Placement. ISPD 2016: 73-80 - [c16]Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo O. Johann, Laleh Behjat:
Routing-Aware Incremental Timing-Driven Placement. ISVLSI 2016: 290-295 - [c15]Mateus Fogaça, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Improving placement algorithms by using visualization tools. NEWCAS 2016: 1-4 - [c14]Jorge L. Tonfat, Guilherme Flach, Ricardo Reis:
Leakage current analysis in static CMOS logic gates for a transistor network design approach. PATMOS 2016: 107-113 - 2015
- [c13]Jucemar Monteiro, Guilherme Flach, Marcelo O. Johann, José Luís Almada Güntzel:
An analytical timing-driven algorithm for detailed placement. LASCAS 2015: 1-4 - [c12]Julia Casarin Puget, Guilherme Flach, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Jezz: An Effective Legalization Algorithm for Minimum Displacement. SBCCI 2015: 19:1-19:5 - [c11]Guilherme Flach, Jucemar Monteiro, Mateus Fogaça, Julia Casarin Puget, Paulo F. Butzen, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
An Incremental Timing-Driven flow using quadratic formulation for detailed placement. VLSI-SoC 2015: 1-6 - 2014
- [j2]Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 546-557 (2014) - [c10]Tania Mara Ferla, Guilherme Flach, Ricardo Reis:
A tool to simulate optical lithography in nanoCMOs. I2MTC 2014: 1471-1474 - 2013
- [c9]Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis:
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. ISCAS 2013: 2549-2552 - [c8]Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis:
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. ISVLSI 2013: 84-89 - 2012
- [j1]Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis:
High-performance clock mesh optimization. ACM Trans. Design Autom. Electr. Syst. 17(3): 33:1-33:17 (2012) - [c7]Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis:
Transistor sizing and gate sizing using geometric programming considering delay minimization. NEWCAS 2012: 85-88 - 2011
- [c6]Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis:
Gate Sizing Minimizing Delay and Area. ISVLSI 2011: 315-316 - [c5]Guilherme Flach, Marcelo O. Johann, Ricardo Reis:
Quadratic placement with single-iteration linear system solver. SBCCI 2011: 109-112 - 2010
- [c4]Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
A Mesh-Buffer Displacement Optimization Strategy. ISVLSI 2010: 282-287
2000 – 2009
- 2007
- [c3]Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis:
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. ISVLSI 2007: 67-72 - [c2]Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis:
Cell placement on graphics processing units. SBCCI 2007: 87-92 - 2006
- [c1]Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis:
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. SBCCI 2006: 220-225
Coauthor Index
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