Article

Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing

Authors:

Renato Hentschke,

Guilherme Flach,

Ricardo ReisAuthors Info & Claims

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

Pages 220 - 225

https://doi.org/10.1145/1150343.1150399

Published: 28 August 2006 Publication History

Abstract

This paper presents a quadratic placement algorithm to be applied for 3D circuits. We formulate the 3D problem to control the area balance and the number of 3D-Vias between tiers. We introduce the z-Cell Shifting operation in order to control the area balance. We also define a new operation for the refinement of the solution called 3D Iterative Refinement, that has a control statement to avoid excessive number of 3D-Vias in order to keep the feasibility of our placement solution. After quadratic placement, we move to the placement legalization that is based on min-cost max flow and Simulated Annealing. For detailed placement refinement, we apply Simulated Annealing without cell migration between tiers. Experimental results show that our placement flow targeting one tier is comparable to academic tools such as FastPlace, Capo and Dragon in wire length and running time when targeting a single tier. On multiple tiers, we can reduce the average wire length from 7% (2 tiers) to 32% (5 tiers) and worst wire length by 26% (2 tiers) to 52% (5 tiers). The number of 3D-Vias obtained is feasible since the area overhead introduced is always below 10%.

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Cited By

Liao PZhao YGuo DLin YYu B(2024)Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334729343:6(1624-1637)Online publication date: Jun-2024
https://doi.org/10.1109/TCAD.2023.3347293
Thorolfsson TLipa SFranzon P(2012)A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integrationProceedings of the IEEE 2012 Custom Integrated Circuits Conference10.1109/CICC.2012.6330589(1-4)Online publication date: Sep-2012
https://doi.org/10.1109/CICC.2012.6330589
Thorolfsson TMoezzi-Madani NFranzon P(2011)Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processorIET Computers & Digital Techniques10.1049/iet-cdt.2009.01065:3(198)Online publication date: 2011
https://doi.org/10.1049/iet-cdt.2009.0106
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Index Terms

Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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cover image ACM Conferences

SBCCI '06: Proceedings of the 19th annual symposium on Integrated circuits and systems design

August 2006

248 pages

ISBN:1595934790

DOI:10.1145/1150343

General Chair:
Claudionor Coelho
Universidade de Minas Gerais, Brazil
,
Program Chairs:
Ricardo Jacobi
Universidade de Brasilia, Brazil
,
Juergen Becker
Universitaet Karlsruhe (TH), Germany

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 28 August 2006

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SBCCI06: 19th Symposium on Integrated Circuits and System Design

August 28 - September 1, 2006

MG, Ouro Preto, Brazil

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Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

Liao PZhao YGuo DLin YYu B(2024)Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU AccelerationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334729343:6(1624-1637)Online publication date: Jun-2024
https://doi.org/10.1109/TCAD.2023.3347293
Thorolfsson TLipa SFranzon P(2012)A 10.35 mW/GFlop stacked SAR DSP unit using fine-grain partitioned 3D integrationProceedings of the IEEE 2012 Custom Integrated Circuits Conference10.1109/CICC.2012.6330589(1-4)Online publication date: Sep-2012
https://doi.org/10.1109/CICC.2012.6330589
Thorolfsson TMoezzi-Madani NFranzon P(2011)Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processorIET Computers & Digital Techniques10.1049/iet-cdt.2009.01065:3(198)Online publication date: 2011
https://doi.org/10.1049/iet-cdt.2009.0106
Thorolfsson TMelamed SDavis WFranzon P(2010)Low-Power Hypercube Divided Memory FFT Engine Using 3D IntegrationACM Transactions on Design Automation of Electronic Systems10.1145/1870109.187011416:1(1-25)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1145/1870109.1870114
Thorolfsson TLuo GCong JFranzon P(2010)Logic-on-logic 3D integration and placement2010 IEEE International 3D Systems Integration Conference (3DIC)10.1109/3DIC.2010.5751451(1-4)Online publication date: Nov-2010
https://doi.org/10.1109/3DIC.2010.5751451
Thorolfsson TMoezzi-Madani NFranzon PHenkel JKeshavarzi AChang NGhani T(2009)A low power 3D integrated FFT engine using hypercube memory divisionProceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design10.1145/1594233.1594289(231-236)Online publication date: 19-Aug-2009
https://dl.acm.org/doi/10.1145/1594233.1594289
Sawicki SWilke GJohann MReis R(2009)A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)10.1109/ICECS.2009.5410761(852-855)Online publication date: Dec-2009
https://doi.org/10.1109/ICECS.2009.5410761
Flach GJohann MHentschke RReis RPetraglia APedroni VCauwenberghs G(2007)Cell placement on graphics processing unitsProceedings of the 20th annual conference on Integrated circuits and systems design10.1145/1284480.1284510(87-92)Online publication date: 3-Sep-2007
https://dl.acm.org/doi/10.1145/1284480.1284510
Goplen BSpatnekar SLevitan S(2007)Placement of 3D ICs with thermal and interlayer via considerationsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278637(626-631)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278637
Sawicki SHentschke RJohann MReis R(2006)Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits2006 13th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2006.379809(399-402)Online publication date: Dec-2006
https://doi.org/10.1109/ICECS.2006.379809

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