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In this work we develop a new quadratic placement technique where we prematurely interrupt the linear system solver to interleave the spreading forces saving runtime. This has low impact in the placement flow due to the expand-contract phenomena ...

Placement based on simulated annealing is in dominant use in the FPGA community due to its superior quality of result (QoR). However, given the progression of FPGA device capacity to the order of 100K LUTs, the long runtime associated with simulated ...

The force-directed quadratic placer ldquoKraftwerk2,rdquo as described in this paper, is based on two main concepts. First, the force that is necessary to distribute the modules on the chip is separated into the following two components: a hold force ...

Graphics Processing Units (GPUs) can be viewed as stream processors and, therefore, can be applied to improve the performance of data-parallel algorithms. GPUs can beat CPUs in most stream-like algorithms and have been successfully applied to solve ...

A placement problem can be formulated as a quadratic program with nonlinear constraints. Those constraints make the problem hard. Omitting the constraints and solving the unconstrained problem results in a placement with substantial cell overlaps. To ...

This paper describes the implementation of a wire length-driven force-directed placer named FDP for generic placement. Specifically, it describes efficient force computation for cell spreading, numerical instabilities during force-directed placement, a ...

This paper presents a quadratic placement algorithm to be applied for 3D circuits. We formulate the 3D problem to control the area balance and the number of 3D-Vias between tiers. We introduce the z-Cell Shifting operation in order to control the area ...

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem ...

Placement is a critical step in VLSI design because it dominates overall speed and quality of design flow. In this paper, a new fast and stable placement algorithm called FaSa is proposed. It uses quadratic programming model and Lagrange ...

We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that ...

Bo ole andivision, and henc eBo ole ansubstitution, produc es better result than algebraic division and substitution. However, due to the lack of an efficient Bo ole andivision algorithm, Bo ole ansubstitution has rarely b een used. We present an ...

We describe a new constructive multilevel logic synthesis system that integrates the traditionally separate technology-independent and technology-dependent stages of modern synthesis tools. Dubbed M32, this system is capable of generating circuits ...

For sequential circuits with given initial states, new equivalent initial states must be computed for retiming, which unfortunately is NP-hard. In this paper we propose a novel polynomial time algorithm for optimal FPGA mapping with forward retiming to ...

In this paper we report a framework that makes it possible for a designer to rapidly explore the application-specific programmable processor design space under area constraints. The framework uses a production-quality compiler and simulation tools to ...

A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiv er is used as a driv er example. Compact descriptions, combined with efficient sim ulationand syn thesis strategies are ...

Optimization at the early stages of design are crucial. However, due to an overwhelming number of design and optimization options, design exploration is often conducted in a qualitative, ad-hoc manner. This paper presents a methodology and interactive ...

It is well understood that frequency independent lumped-element circuits can be used to accurately model proximity and skin effects in transmission lines [7]. Furthermore, it is also understood that these circuits can be synthesized knowing only the ...

As VLSI circuit speeds have increased, reliable chip and system design can no longer be performed without accurate three-dimensional interconnect models. In this paper, we describe an integral equation aproach to modeling the impedance of inter-connect ...

This paper presents a layout extraction and verification methodology which targets reliability-driven I/O design for CMOS VLSI chip, specifically to guard against electrostatic discharge (ESD) stress and latchup. We propose a new device extraction ...

This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the ground bounce, but to distribute it more evenly among the pads while the ...