"High throughput architecture for packet classification using FPGA."

Tao Zhang et al. (2009)

> Home

Details and statistics

DOI: 10.1145/1882486.1882500

access: closed

type: Conference or Workshop Paper

metadata version: 2021-11-16

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ancs/ZhangWZY09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ancs/ZhangWZY09
Tao Zhang, Yonggang Wang, Lijun Zhang, Yang Yang:
High throughput architecture for packet classification using FPGA. ANCS 2009: 62-63

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.