"Race logic synthesis for a multithreaded HDL/ESL simulator for SoC designs."

Terence Chan (2010)

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DOI: 10.1109/APCCAS.2010.5774986

access: closed

type: Conference or Workshop Paper

metadata version: 2019-11-29

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Terence Chan:
Race logic synthesis for a multithreaded HDL/ESL simulator for SoC designs. APCCAS 2010: 1179-1182

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