"Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator ..."

Kwen-Siong Chong et al. (2019)

> Home

Details and statistics

DOI: 10.1109/ASIANHOST47458.2019.9006690

access: closed

type: Conference or Workshop Paper

metadata version: 2024-11-12

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asianhost/ChongSLKHWZGC19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asianhost/ChongSLKHWZGC19
Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang:
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells. AsianHOST 2019: 1-7

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.