"High speed layout synthesis for minimum-width CMOS logic cells via Boolean ..."

Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada (2004)

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DOI: 10.1109/ASPDAC.2004.110

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. ASP-DAC 2004: 149-154

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