"Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel ..."

Zihang Ma et al. (2024)

> Home

Details and statistics

DOI: 10.1109/ASP-DAC58780.2024.10473990

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/aspdac/MaLW0YW24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/aspdac/MaLW0YW24
Zihang Ma, Zeyu Li, Yuanfang Wang, Yu Li, Jun Yu, Kun Wang:
Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier. ASPDAC 2024: 527-532

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.